Spiking neural network (SNN) can process discrete spikes and offers a high degree of real-time performance and excellent energy efficiency ratio. However, most current neuromorphic hardware platforms lack efficient driven algorithms and only support a single type of neuron model, which has slow speed and poor scalability. This paper proposes a general FPGA-based neuromorphic hardware acceleration platform (FPGA-NHAP), supporting the effective inference and acceleration of SNN network with low power, high speed and good scalability. First, a neuron computing unit is designed to simulate the both LIF and Izhikevich (IZH) neurons with the parallel spike caching and scheduling technique. Second, a novel integrated driven update algorithm is proposed to complete the spike encoding of external data, reducing the waiting time of neuron state update effectively. Third, the proposed platform is implemented using a RISC-V processor and a Xilinx FPGA, simulating 16,384 neurons and 16.8 million synapses with a power consumption of 0.535 W. Finally, two different three-layer SNN networks are deployed on the proposed platform for recognition tasks on the MNIST and Fashion-MNIST datasets, achieving the accuracy of 97.70%, 85.14% (LIF) and 97.81%, 83.16% (IZH), frame rates of 208 frame/s, 128 frame/s (LIF) and 206 frame/s, 141 frame/s (IZH), respectively.

Spiking neural network (SNN) has attracted extensive attention in large-scale image processing tasks. To obtain higher computing efficiency, the development of hardware architecture suitable for SNN computing has become a hot research topic. However, the existing hardware of spike neurons still has high computational complexity and they do not perform well enough on complicated datasets, and the neuromorphic system cannot support SNNs with different convolutional topologies, resulting in low efficiency of the system. To address the above problems, an optimized leaky integrated-and-fire (LIF) neuron called EPC-LIF and a neuromorphic hardware acceleration system (ELIF-NHAS) are designed and implemented based on the field-programmable gate array (Xilinx Kintex-7). First, the classical LIF neuron is designed using the optimization method of extended prediction correction (EPC), which can reduce the computation complexity and hardware resources with a maximum frequency of 439.95 MHz. The ELIF-NHAS is constructed and optimized with parallel and pipeline techniques for effectively running SNNs, working with a maximum frequency of 135.6 MHz. Then, the genetic algorithm is applied to adjust the membrane threshold of neurons for further improving the accuracy of SNNs. Furthermore, the ELIF-NHAS can support different SNNs with multilayer perceptron and convolutional neural network topologies (called SCNN), including traditional, depth-separate, and residual convolutions. The accuracy of multilayer SCNNs can achieve 99.10%, 90.29%, and 82.15% on MNIST, Fashion-MNIST, and SVHN datasets, respectively; and the speed and energy consumption achieve 1.21 ms/image and 1.19 mJ/image. Compared with existing systems, the ELIF-NHAS is more suitable for the deployment and inference of SNNs with higher speed and lower consumption.

Currently, the performance of spiking neural networks (SNNs) under complicated tasks is gradually close to that of convolutional neural networks (CNNs). However, the existing neuromorphic computing hardware architectures (NCHAs) for accelerating SNNs lack effective sparse detection and cannot realize effective spatio-temporal parallel computing, resulting in high inference latency. In this paper, we propose an improved neuromorphic computing hardware architecture (called SiBrain) with high accuracy, low power and low latency, consisting of a sparse spatio-temporal parallel processing element (S $^{2}$ TP-PE) array for spike convolution and pooling computation and a fully-connected (FC) Core for spike FC computation. In the novel S $^{2}$ TP-PE array, a S $^{2}$ TP computation unit is designed by using time-step and channel parallel computation techniques to reduce the latency caused by multiple time-steps of SNN, and a sparse detection and response unit is presented based on channel-cache and block-multiplex to achieve the spike detection, response, and reuse. Combining the above kernel components, the SiBrain is built and implemented on Virtex-7 FPGA with 200MHz. The experimental results show that the SiBrain can effectively support the deployment of SCNN models with different sizes, and the deployed large-scale Spiking Visual-Geometry-Group (VGG) model can achieve the recognition accuracies of 90.25% and 66.97% on CIFAR-10 and CIFAR-100 with the power consumption of 1.5 W and the energy efficiency of 83 GSOPs/W. Compared with existing FPGA-based SNN accelerators, SiBrain has a maximum increase in inference speed of nearly 11 times and a maximum decrease in energy consumption of nearly 34 times, respectively.

Most of the existing methods for traffic sign recognition exploited deep learning technology such as convolutional neural networks (CNNs) to achieve a breakthrough in detection accuracy; however, due to the large number of CNN’s parameters, there are problems in practical applications such as high power consumption, large calculation, and slow speed. Compared with CNN, a spiking neural network (SNN) can effectively simulate the information processing mechanism of biological brain, with stronger parallel processing capability, better sparsity, and real-time performance. Thus, we design and realize a novel traffic sign recognition system [called SNN on FPGA-traffic sign recognition system (SFPGA-TSRS)] based on spiking CNN (SCNN) and FPGA platform. Specifically, to improve the recognition accuracy, a traffic sign recognition model spatial attention SCNN (SA-SCNN) is proposed by combining LIF/IF neurons based SCNN with SA mechanism; and to accelerate the model inference, a neuron module is implemented with high performance, and an input coding module is designed as the input layer of the recognition model. The experiments show that compared with existing systems, the proposed SFPGA-TSRS can efficiently support the deployment of SCNN models, with a higher recognition accuracy of 99.22%, a faster frame rate of 66.38 frames per second (FPS), and lower power consumption of 1.423 W on the GTSRB dataset.

A Trusted Execution Environment (TEE) is an efficient way to secure information. To obtain higher efficiency, the building of a dual-core system-on-chip (SoC) with TEE security capabilities is the hottest topic. However, TEE SoCs currently commonly use complex processor cores such as Rocket, resulting in high resource usage. More importantly, the cryptographic unit lacks flexibility and ignores secure communication in dual cores. To address the above problems, we propose DITES, a dual-core TEE SoC based on a Reduced Instruction Set Computer-V (RISC-V). At first, we designed a fully isolated multi-level bus architecture based on a lightweight RISC-V processor with an integrated crypto core supporting Secure Hashing Algorithm-1 (SHA1), Advanced Encryption Standard (AES), and Rivest–Shamir–Adleman (RSA), among which RSA can be configured to five key lengths. Then, we designed a secure boot based on Chain-of-Trust (CoT). Furthermore, we propose a hierarchical access policy to improve the security of inter-core communication. Finally, DITES is deployed on a Kintex 7 Field-Programmable-Gate-Array (FPGA) with a power consumption of 0.297 W, synthesized using TSMC 90 nm. From the results, the acceleration ratios of SHA1 and RSA1024 decryption/encryption can reach 75 and 1331/1493, respectively. Compared to exiting TEE SoCs, DITES has lower resource consumption, higher flexibility, and better security.

Recently, the design of spiking neural networks (SNNs) processors based on FPGA have become a hot research topic for their low power and high efficiency. However, most existing works lack flexibility in configuration to accomplish efficient computation of deep SNNs with different network structures (e.g., residuals). In this brief, a high-performance general spiking convolution processing unit and the corresponding hardware architecture (named SCPU) is designed to support both standard and residual convolution; then, a neuromorphic processor containing SCPU (called FPGA-SCPP) is implemented on Xilinx Virtex-7 FPGA. Specifically, the model parameters are fused and quantified to reduce the computational amounts and simplify its hardware implementation. And a spike event processing unit is designed based on event computation and direct data flow to complete the standard and residual convolution computations. The experimental results show the FPGA-SCPP can effectively deploy different large-scale SNNs models such as VGG and ResNet, with the highest recognition accuracies of 92.45% and 68.55% on CIFAR-10/CIFAR-100, respectively. Our FPGA-SCPP has a computational power of only 1.7W and a frame rate of 40fps, which improves inference speed by about 6 times and reduces power consumption by 3 times compared to existing processors. Therefore, FPGA-SCPP can effectively accomplish the acceleration of deep SNNs, especially for models with spiking residual blocks.