Spiking neural network (SNN) can process discrete spikes and offers a high degree of real-time performance and excellent energy efficiency ratio. However, most current neuromorphic hardware platforms lack efficient driven algorithms and only support a single type of neuron model, which has slow speed and poor scalability. This paper proposes a general FPGA-based neuromorphic hardware acceleration platform (FPGA-NHAP), supporting the effective inference and acceleration of SNN network with low power, high speed and good scalability. First, a neuron computing unit is designed to simulate the both LIF and Izhikevich (IZH) neurons with the parallel spike caching and scheduling technique. Second, a novel integrated driven update algorithm is proposed to complete the spike encoding of external data, reducing the waiting time of neuron state update effectively. Third, the proposed platform is implemented using a RISC-V processor and a Xilinx FPGA, simulating 16,384 neurons and 16.8 million synapses with a power consumption of 0.535 W. Finally, two different three-layer SNN networks are deployed on the proposed platform for recognition tasks on the MNIST and Fashion-MNIST datasets, achieving the accuracy of 97.70%, 85.14% (LIF) and 97.81%, 83.16% (IZH), frame rates of 208 frame/s, 128 frame/s (LIF) and 206 frame/s, 141 frame/s (IZH), respectively.

Spiking neural network (SNN) has attracted extensive attention in large-scale image processing tasks. To obtain higher computing efficiency, the development of hardware architecture suitable for SNN computing has become a hot research topic. However, the existing hardware of spike neurons still has high computational complexity and they do not perform well enough on complicated datasets, and the neuromorphic system cannot support SNNs with different convolutional topologies, resulting in low efficiency of the system. To address the above problems, an optimized leaky integrated-and-fire (LIF) neuron called EPC-LIF and a neuromorphic hardware acceleration system (ELIF-NHAS) are designed and implemented based on the field-programmable gate array (Xilinx Kintex-7). First, the classical LIF neuron is designed using the optimization method of extended prediction correction (EPC), which can reduce the computation complexity and hardware resources with a maximum frequency of 439.95 MHz. The ELIF-NHAS is constructed and optimized with parallel and pipeline techniques for effectively running SNNs, working with a maximum frequency of 135.6 MHz. Then, the genetic algorithm is applied to adjust the membrane threshold of neurons for further improving the accuracy of SNNs. Furthermore, the ELIF-NHAS can support different SNNs with multilayer perceptron and convolutional neural network topologies (called SCNN), including traditional, depth-separate, and residual convolutions. The accuracy of multilayer SCNNs can achieve 99.10%, 90.29%, and 82.15% on MNIST, Fashion-MNIST, and SVHN datasets, respectively; and the speed and energy consumption achieve 1.21 ms/image and 1.19 mJ/image. Compared with existing systems, the ELIF-NHAS is more suitable for the deployment and inference of SNNs with higher speed and lower consumption.

Currently, the performance of spiking neural networks (SNNs) under complicated tasks is gradually close to that of convolutional neural networks (CNNs). However, the existing neuromorphic computing hardware architectures (NCHAs) for accelerating SNNs lack effective sparse detection and cannot realize effective spatio-temporal parallel computing, resulting in high inference latency. In this paper, we propose an improved neuromorphic computing hardware architecture (called SiBrain) with high accuracy, low power and low latency, consisting of a sparse spatio-temporal parallel processing element (S $^{2}$ TP-PE) array for spike convolution and pooling computation and a fully-connected (FC) Core for spike FC computation. In the novel S $^{2}$ TP-PE array, a S $^{2}$ TP computation unit is designed by using time-step and channel parallel computation techniques to reduce the latency caused by multiple time-steps of SNN, and a sparse detection and response unit is presented based on channel-cache and block-multiplex to achieve the spike detection, response, and reuse. Combining the above kernel components, the SiBrain is built and implemented on Virtex-7 FPGA with 200MHz. The experimental results show that the SiBrain can effectively support the deployment of SCNN models with different sizes, and the deployed large-scale Spiking Visual-Geometry-Group (VGG) model can achieve the recognition accuracies of 90.25% and 66.97% on CIFAR-10 and CIFAR-100 with the power consumption of 1.5 W and the energy efficiency of 83 GSOPs/W. Compared with existing FPGA-based SNN accelerators, SiBrain has a maximum increase in inference speed of nearly 11 times and a maximum decrease in energy consumption of nearly 34 times, respectively.

The emergence of deep learning technology has significantly improved the performance of super-resolution algorithms for a single remote sensing image; however, the number of deep learning model parameters is large, which limits its real-time deployment. In addition, the reconstructed image quality still needs improvement. To deal with the aforementioned problems, a lightweight multi-scale residual attention information distillation network (MRA-IDN) is proposed in this paper. It achieves high quality and fast super-resolution processing of remote sensing images. First, a high and low frequency separation reconstruction strategy is adopted that enables the network to improve the reconstructed details of high frequency components while keeping the number of model parameters low. Second, a novel multi-scale residual attention information distillation group (MRA-IDG) is designed as the key component to further extract richer regional features with different perceptual fields and high frequency information while reducing the number of network parameters. This is achieved by combining a multi-scale residual information distillation (MSR-ID) block that consists of multiple residual convolutional sub-blocks (RCBs) and a high frequency channel aware (HFCA) attention block. Last, the experimental results show that, compared with existing mainstream methods such as the MHAN, the number of model parameters can be reduced by 75%, and the edge details of the reconstructed images are richer and more complete. The corresponding PSNR and SSIM can reach 31.59 dB and 0.824, respectively, under the condition of a ×4 magnification factor, and 27.39 dB and 0.668, respectively, under the condition of a ×8 magnification factor.