Recent mm-wave PLLs have explored different architectures to enhance their jitter performance at low power. Without noisy loop components, the injection-locked PLL in [1] using a GHz reference (REF=2.25GHz) can effectively suppress the integrated jitter (86fs _rms ), resulting in a better jitter-power FoM (-247.2dB). Yet, high-frequency REF injection leads to large spur (-32dBc), entailing continuous frequency tracking to withstand the PVT variations. Also, at the system level, the GHz REF has to be generated on-chip (i.e. cascaded PLLs). The power overhead, e.g., additional 20mW in [2], and unwanted coupling between the two VCOs become inevitable. To this end, direct-synthesis mm-wave PLLs using a MHz REF are of higher interest, despite the challenge of a large division ratio (N). An example is a Type-II mm-wave PLL reported in [3] that achieves 115fsrms integrated jitter, but the involved divider, charge pump (CP), and VCO totally draw 31mW to suppress the in-band and out-of-band phase noise (PN).

This letter presents a type-I Narrow-Pulse-Sampling (NPS) phase-locked loop (PLL). It features a circuit technique: NPS phase detector + T-shape switch, to address the main spurrelated non-idealities. Fabricated in 28-nm CMOS, the NPS-PLL operating at 3.3 GHz measures a -78.7-dBc reference spur and a -128.1-dBc/Hz absolute in-band phase noise at 1-MHz offset for a jitter-power Figure-of-Merit (FOM) of -254 dB, without the need of calibration and reference buffer.

This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fs _RMS , and a spur level of -63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of -241.9 dB. With a 103-MHz reference input, a bandwidth of ~20 MHz aids suppressing significantly the ring VCO's phase noise (PN), leading to an in-band PN of -116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm ² .

This paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency. Unlike the typical type-II single-loop PLL using a tri-state phase-frequency detector (PFD) plus a charge pump (CP) that has several limits in high-speed operation, our proposed PLL features a dual-loop scheme to enhance its performance and operating speed at low power. Specifically, we propose a dynamic frequency detector (FD) and a phase detector (PD) in conjunction with voltage-to-current converters (VICs) to avoid the typical current-mode-logic (CML) circuitry for static power reduction. Prototyped in 65-nm CMOS process, the entire PLL dissipates 10.6 mW, of which the dynamic FD and PD merely consume 0.28 mW. The integrated jitter is 415.6 fsrms (10 kHz to 100 MHz) and the reference spur level is -53 dBc at a 26.4-GHz output.

This brief describes an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) incorporating a push–pull sub-sampling phase detector to significantly suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and a low-power fast-locking frequency-locked loop (FLL) to shorten the settling time. Prototyped in 65-nm CMOS, the SS-PLL at 3.3 GHz shows a reference spur of −82.2 dBc, an integrated jitter of 64.9 fs _rms (1 kHz to 40 MHz), and an in-band phase noise (PN) of −128.4 dBc/Hz at 1-MHz offset. The corresponding jitter power figure of merit (FOM) is −255 dB. The entire SS-PLL consumes 7.5 mW, with only $90~\mu \text{W}$ associated with the FLL.

The common self-oscillation-mode (SOM) frequency dividers have a high-Q sensitivity curve limiting the locking range (LR). This letter reports a non-SOM (NSOM) frequency divider-by-2. Fabricated in 65-nm CMOS, it occupies a die area of 6.5 × 7 μm ² , and measures a single-band untuned LR of 166.6% (4-44 GHz), over a small input range <;0.15 Vpp. The key technique is a load-modulated dynamic latch aided by a current-reuse cross-coupled pMOS pair. The achieved figure-of-merit of 26.6 GHz/mW compares favorably with the state-of-the-art.