A 0.016-mm² 144-μ W three-stage amplifier capable of driving 1-to-15-nF capacitive load (C_L) is described. It is optimized via combining current-buffer Miller compensation and parasitic-pole cancellation (via an active left-half-plane zero circuit) to extend the C_L drivability with small power and area. Fabricated in 0.35-μ m CMOS, the minimum gain-bandwidth product (GBW), slew rate (SR) and phase margin measured over 1-to-15-nF C_L are 0.95 MHz, 0.22 V/ μs and 52.3 °, respectively. The results at 15-nF C_L correspond to 2.02x-improved small-signal FOM_S (=GBW·C_L/Power), and 1.44x-improved large-signal FOM_L (=SR·C_L/Power) with respect to prior art. The sizing and optimization are systematically guided by Local Feedback Loop Analysis. It is an insightful control-centric method allowing the pole-zero placements to be more analyzable and comparable at the system level.

This article proposes a single-stage inductive-power-transfer (IPT) converter operating as a wireless constant-power (CP) and maximum-efficiency battery charger. By maintaining a constant output power rather than providing a constant output current throughout the dominant stage of battery charging, the IPT converter can make the utmost of its power capability, thus having a faster charging rate. The proposed single-stage IPT converter adopts series-series compensation and includes a switch-controlled capacitor (SCC) and a semiactive rectifier (SAR) in the secondary side. Manipulating the SCC and the SAR to emulate the optimum impedance of the resonator and the load, we propose a novel operation approach combining the merits of load-independent transfer characteristic and load impedance matching, to achieve a simple solution to CP charging and maximum efficiency throughout the charging process. Since the control scheme is based on fixed operating frequency and secondary-side real-time regulation, wireless feedback communication is not required. Moreover, soft switching and low voltage stress can be easily achieved in this IPT converter.

A self-body-biasing technique is proposed for differential-drive cross-coupled (DDCC) rectifier, with its profound application in far-field RF energy-harvesting systems. The conventional source-to-body, and the proposed technique known as Lower DC Feeding (LDCF), were fabricated in the 130-nm CMOS and compared at the operation frequency of 500 MHz, 953 MHz and 2 GHz along with a corresponding load of 2 kΩ, 10 kΩ and 50 kΩ. The technique allows the PMOS transistors to operate with a dynamic threshold voltage (Vth) which improves the power conversion efficiency (PCE) when the rectifier is operating at a smaller received power. A 9.5% of improvement is achieved at the peak PCE when the rectifier is operating at 953 MHz, and driving a 10 kΩ load. A maximum PCE of 73.9% is measured at 2 GHz when driving a 2-kΩ load. The LDCF technique also offers a self-limiting capability for its output voltage, by reducing the PCE at larger received power. A limit-voltage level of 3.5 V is measured irrespective to the operating frequency and load. This capability aids the protection of the subsequent circuits in a wireless sensor from being overpowered.

In this paper, an ultra-compact single-chip solar energy harvesting IC using on-chip solar cell for biomedical implant applications is presented. By employing an on-chip charge pump with parallel connected photodiodes, a 3.5× efficiency improvement can be achieved when compared with the conventional stacked photodiode approach to boost the harvested voltage while preserving a single-chip solution. A photodiode-assisted dual startup circuit (PDSC) is also proposed to improve the area efficiency and increase the startup speed by 77%. By employing an auxiliary charge pump (AQP) using zero threshold voltage (ZVT) devices in parallel with the main charge pump, a low startup voltage of 0.25 V is obtained while minimizing the reversion loss. A 4 V _in gate drive voltage is utilized to reduce the conduction loss. Systematic charge pump and solar cell area optimization is also introduced to improve the energy harvesting efficiency. The proposed system is implemented in a standard 0.18-μm CMOS technology and occupies an active area of 1.54 mm ² . Measurement results show that the on-chip charge pump can achieve a maximum efficiency of 67%. With an incident power of 1.22 mW/cm ² from a halogen light source, the proposed energy harvesting IC can deliver an output power of 1.65 μW at 64% charge pump efficiency. The chip prototype is also verified using in-vitro experiment.