We present a systematic study on the gate length ( ${L}_{{g}}\text {)}$ scaling behavior and the impact of the side-recess spacing ( ${L}_{\text {side}}\text {)}$ on dc and high-frequency characteristics of In0.8Ga0.2As quantum-well (QW) high-electron-mobility transistors (HEMTs) with ${L}_{{g}}$ from 10 $\mu $ m to 20 nm, for the purpose of understanding the scaling limit of maximum oscillation frequency ( ${f}_{\text {max}}\text {)}$ and thereby demonstrating terahertz devices. The fabricated In0.8Ga0.2As QW HEMTs with ${L}_{{g}} =20$ nm and ${L}_{\text {side}} =150$ nm exhibited values of drain-induced-barrier-lowering (DIBL) of 60 mV/V, current-gain cutoff frequency ( ${f}_{{T}}\text {)}$ of 0.75 THz, and ${f}_{\text {max}}$ of 1.1 THz, while the device with ${L}_{\text {side}} =50$ nm showed DIBL of 110 mV/V and ${f}_{{T}}$ / ${f}_{\text {max}}$ of 0.72/0.53 THz. It was central to strictly control short-channel effects (SCEs) from the perspective of DIBL to maximize the improvement of ${f}_{\text {max}}$ , as ${L}_{{g}}$ was scaled down deeply. In an effort to understand the ${L}_{{g}}$ scaling behavior of ${f}_{\text {max}}$ , we carried out the small-signal modeling for both types of devices and found that the increase of the intrinsic output conductance ( ${g}_{\text {oi}}\text {)}$ played a critical role in determining ${f}_{\text {max}}$ in short- ${L}_{{g}}$ HEMTs. On the contrary, the fabricated devices with ${L}_{\text {side}} =150$ nm exhibited a tight control of SCEs at ${L}_{{g}}$ of 20 nm. As a result, ${f}_{\text {max}}$ in those devices was boosted to 1.1 THz, and more importantly this high ${f}_{\text {max}}$ was maintained even as ${L}_{{g}}$ was scaled down to 20 nm. The results in this work represent the best balance of ${f}_{{T}}$ and ${f}_{\text {max}}$ in any transistor technology on any material system, displaying both ${f}_{{T}}$ and ${f}_{\text {max}}$ in excess of 700 GHz simultaneously.

We present sub-30-nm In _0.8 Ga _0.2 As composite-channel high-electron-mobility transistors (HEMTs) with outstanding dc and high-frequency characteristics. We adopted a composite-channel design with an In _0.8 Ga _0.2 As core layer, which led to superior carrier transport properties such as a Hall mobility ( μ _{n_Hall} ) of 13500 cm ² / V·s. The device with L _g = 19 nm exhibited an excellent combination of dc and RF properties, including R _ON = 271Ω-μm, g _{m_max} = 2.8 mS / μm, and f _T / f _max = 738 / 492 GHz. To understand the physical origin of such an excellent combination of dc and RF responses, we analyzed the effective mobility ( μ _{n_eff} ) and delay time for both long- and short- L _g devices, revealing a very high μ _{n_eff} value of 13200 cm ² / V·s and an average velocity under the gate ( v _avg ) of 6.2×10 ⁷ cm / s. We also studied the impact of the electrostatic integrity of the device, finding that the intrinsic output conductance (g _oi ) played a role in determining f _T and f _max in short- L _g HEMTs.

Conventional techniques to characterize the carrier transport properties in high-electron-mobility transistors do not account for the effect of each individual unit process and device integration, and can be challenging to use for short-channel devices. To overcome this, we have developed a new technique that consists of measurement and analysis of the transconductance scaling behavior. The proposed ${g}_{m}$ modeling technique yielded the effective mobility, $\mu _{n\_{}{\textit {eff}}}$ , and saturation velocity, ${v}_{\textit {sat}}$ for fabricated InxGa $_{{1}-{x}}$ As Quantum-Well (QW) HEMTs, correlating the carrier transport properties to the device characteristics. This helps illuminate the physics of the carrier transport properties of HEMTs from the mobility relevant to the velocity saturation regimes.

We investigated the impact of a sulfur passivation (S-passivation) process step on carrier transport properties of surface-channel In _0.7 Ga _0.3 As quantum-well (QW) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) with source/drain (S/D) regrowth contacts. To do so, we fabricated long-channel In _0.7 Ga _0.3 As QW MOSFETs with and without (NH ₄ ) ₂ S treatment prior to a deposition of Al ₂ O ₃ /HfO ₂ = 1-nm/3-nm by atomic-layer-deposition (ALD). The devices with S-passivation exhibited a lower value of subthreshold-swing (S) = 74 mV/decade and more positive shift in the threshold voltage (VT) than those without S-passivation. From the perspective of carrier transport, S-passivated devices displayed excellent effective mobility (μ _eff ) in excess of 6,300 cm ² /V·s at 300 K. It turned out that the improvement of μ _eff was attributed to reduced Coulombic and surface-roughness scatterings. Using a conductance method, a fairly small value of interface trap density (D _it ) = 1.56 × 10 ¹² cm ^-2 eV ^-1 was obtained for the devices with S-passivation, which was effective in mitigating the Coulombic scattering at the interface between the high-k dielectric layer and the In _0.7 Ga _0.3 As surface-channel layer.

We present a fully analytical model and physical investigation on the source resistance (R_S) in In_xGa_1−xAs quantum-well high-electron mobility transistors based on a three-layer TLM system. The R_S model in this work was derived by solving the coupled quadratic differential equations for each current component with appropriate boundary conditions, requiring only six physical and geometrical parameters, including ohmic contact resistivity (ρ_c), barrier tunneling resistivity (ρ_barrier), sheet resistances of the cap and channel regions (R_{sh_cap} and R_{sh_ch}), side-recessed length (L_side) and gate-to-source length (L_gs). To extract each model parameter, we fabricated two different TLM structures, such as cap-TLM and recessed-TLM. The developed R_S model in this work was in excellent agreement with the R_S values measured from the two TLM devices and previously reported short-L_g HEMT devices. The findings in this work revealed that barrier tunneling resistivity already played a critical role in reducing the value of R_S in state-of-the-art HEMTs. Unless the barrier tunneling resistivity is reduced considerably, innovative engineering on the ohmic contact characteristics and gate-to-source spacing would only marginally improve the device performance.