We present our latest results on L g = 87 nm InAlAs/InGaAs high-electron-mobility transistors with an excellent combination of dc and high-frequency characteristics. We obtained a maximum transconductance of 3 S/mm at V DS = 0.9 V, an ON-resistance of 273 Ω-μm, a current gain cutoff frequency of 559 GHz, and a maximum oscillation frequency of 671 GHz. According to small-signal modeling, these outstanding device metrics are a consequence of the indium-rich InGaAs channel with very high Hall mobility, compact device design with L SD = 1 μm, and an optimized gate process that yields well-tempered behavior.
In this paper, we investigated the impact of the source-to-drain spacing (LSD) on the DC and high-frequency characteristics of indium-rich In0.8Ga0.2As/In0.52Al0.48As high-electron mobility transistors (HEMTs) on a 3-inch InP substrate. Lg = 87 nm HEMTs with different values of the LSD were fabricated ranging from 1.55 μm to 0.8 μm, and their DC and RF responses were measured and analyzed in detail. In order to suppress the increase of the parasitic gate capacitance, we maintained the gate stem height as high as 200 nm in our device fabrication. Both the maximum transconductance (gm_max) and on-resistance (RON) improved as the LSD scaled down to 0.8 μm. At the same time, the high-frequency figures of the merit (FOMs), such as current-gain cutoff frequency (fT) and maximum oscillation frequency (fmax), increased with the reduction of the LSD. These improvements are attributed to the reduction of series resistances. In particular, the Lg = 87 nm device with an LSD = 0.8 μm exhibited an excellent combination of DC and RF characteristics, such as gm_max = 2.7 mS/μm, RON = 318 Ω-μm, fT = 519 GHz and fmax = 645 GHz, respectively. The results obtained in this work indicate that the reduction of the LSD down to 0.8 μm continues to improve both the DC and RF characteristics of the InGaAs/InAlAs HEMTs, and a possible increase in parasitic capacitance components, associated with a T-shaped, is still negligible in our device architecture.
10 January 2023 in IEEE Transactions on Electron Devices
We present a systematic study on the gate length ( ${L}_{{g}}\text {)}$ scaling behavior and the impact of the side-recess spacing ( ${L}_{\text {side}}\text {)}$ on dc and high-frequency characteristics of In0.8Ga0.2As quantum-well (QW) high-electron-mobility transistors (HEMTs) with ${L}_{{g}}$ from 10 $\mu $ m to 20 nm, for the purpose of understanding the scaling limit of maximum oscillation frequency ( ${f}_{\text {max}}\text {)}$ and thereby demonstrating terahertz devices. The fabricated In0.8Ga0.2As QW HEMTs with ${L}_{{g}} =20$ nm and ${L}_{\text {side}} =150$ nm exhibited values of drain-induced-barrier-lowering (DIBL) of 60 mV/V, current-gain cutoff frequency ( ${f}_{{T}}\text {)}$ of 0.75 THz, and ${f}_{\text {max}}$ of 1.1 THz, while the device with ${L}_{\text {side}} =50$ nm showed DIBL of 110 mV/V and ${f}_{{T}}$ / ${f}_{\text {max}}$ of 0.72/0.53 THz. It was central to strictly control short-channel effects (SCEs) from the perspective of DIBL to maximize the improvement of ${f}_{\text {max}}$ , as ${L}_{{g}}$ was scaled down deeply. In an effort to understand the ${L}_{{g}}$ scaling behavior of ${f}_{\text {max}}$ , we carried out the small-signal modeling for both types of devices and found that the increase of the intrinsic output conductance ( ${g}_{\text {oi}}\text {)}$ played a critical role in determining ${f}_{\text {max}}$ in short- ${L}_{{g}}$ HEMTs. On the contrary, the fabricated devices with ${L}_{\text {side}} =150$ nm exhibited a tight control of SCEs at ${L}_{{g}}$ of 20 nm. As a result, ${f}_{\text {max}}$ in those devices was boosted to 1.1 THz, and more importantly this high ${f}_{\text {max}}$ was maintained even as ${L}_{{g}}$ was scaled down to 20 nm. The results in this work represent the best balance of ${f}_{{T}}$ and ${f}_{\text {max}}$ in any transistor technology on any material system, displaying both ${f}_{{T}}$ and ${f}_{\text {max}}$ in excess of 700 GHz simultaneously.
8 January 2021 in IEEE Transactions on Electron Devices
We present sub-30-nm In 0.8 Ga 0.2 As composite-channel high-electron-mobility transistors (HEMTs) with outstanding dc and high-frequency characteristics. We adopted a composite-channel design with an In 0.8 Ga 0.2 As core layer, which led to superior carrier transport properties such as a Hall mobility ( μ n_Hall ) of 13500 cm 2 / V·s. The device with L g = 19 nm exhibited an excellent combination of dc and RF properties, including R ON = 271Ω-μm, g m_max = 2.8 mS / μm, and f T / f max = 738 / 492 GHz. To understand the physical origin of such an excellent combination of dc and RF responses, we analyzed the effective mobility ( μ n_eff ) and delay time for both long- and short- L g devices, revealing a very high μ n_eff value of 13200 cm 2 / V·s and an average velocity under the gate ( v avg ) of 6.2×10 7 cm / s. We also studied the impact of the electrostatic integrity of the device, finding that the intrinsic output conductance (g oi ) played a role in determining f T and f max in short- L g HEMTs.
26 February 2021 in Journal of the Korean Physical Society
We investigated the impact of a sulfur passivation (S-passivation) process step on carrier transport properties of surface-channel In 0.7 Ga 0.3 As quantum-well (QW) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) with source/drain (S/D) regrowth contacts. To do so, we fabricated long-channel In 0.7 Ga 0.3 As QW MOSFETs with and without (NH 4 ) 2 S treatment prior to a deposition of Al 2 O 3 /HfO 2 = 1-nm/3-nm by atomic-layer-deposition (ALD). The devices with S-passivation exhibited a lower value of subthreshold-swing (S) = 74 mV/decade and more positive shift in the threshold voltage (VT) than those without S-passivation. From the perspective of carrier transport, S-passivated devices displayed excellent effective mobility (μ eff ) in excess of 6,300 cm 2 /V·s at 300 K. It turned out that the improvement of μ eff was attributed to reduced Coulombic and surface-roughness scatterings. Using a conductance method, a fairly small value of interface trap density (D it ) = 1.56 × 10 12 cm -2 eV -1 was obtained for the devices with S-passivation, which was effective in mitigating the Coulombic scattering at the interface between the high-k dielectric layer and the In 0.7 Ga 0.3 As surface-channel layer.