In this paper, for the first time, we designed and analyzed channels between a graphic processing unit and memory in a silicon interposer for a 3-D stacked high bandwidth memory (HBM). We thoroughly analyzed and verified the electrical characteristics of the silicon interposer considering various design parameters, such as the channel width and space, redistribution layer via, and under bump metallurgy pads. In particular, we also considered the meshed ground planes used for the proposed transmission lines, which are microstrip and strip lines. Signal integrity (SI) of the proposed channels in the silicon interposer was successfully analyzed and verified using a full 3-D electromagnetic solver and circuit simulations. Based on the extracted lumped circuit resistance, inductance, conductance and capacitance parameters, we thoroughly analyzed the channel characteristics and identified the parameters that dominantly affect SI in relation to each frequency range. From the analyzed insertion loss and far end crosstalk, we verified SI of the silicon interposer by eye-diagram simulations in terms of eye-height voltage and timing jitter in the time domain. In the worst case, the eye-height voltage and timing jitter of the proposed microstrip lines are 0.911 V and 36.8 ps, respectively, with 72 mV of signal coupling. The eye-height voltage and timing jitter of the proposed strip line are 0.887 V and 42.1 ps with 34 mV of single couplings. We show that the proposed channels of the silicon interposer can successfully transfer data at a 2-Gb/s data rate. Finally, we propose concepts and solutions for the next-generation HBM interface with higher data rates up to 8 Gb/s.

In this article, we propose a processing-in-memory of high bandwidth memory (PIM-HBM) scheme including system architecture and hardware structure. The proposed scheme embeds processing units into the logic layer of the high bandwidth memory (HBM) to expose an excess dynamic random access memory (DRAM) bandwidth. With parallelized DRAM architecture and a high-speed through-silicon via (TSV) structure, the proposed scheme successfully extends the DRAM bandwidth of processing-in-memory (PIM). Also, the total energy consumption is decreased by the reduced interconnection and capacitance-reduced channel structure. We designed the overall architecture and structure with physical feasibility for application to the current HBM. The logic layer and DRAM layers in the HBM are configured to embed the processing units and parallelize the DRAM channels. For high-speed data transfer with low interconnect energy, the TSV and silicon interposer channels are designed and analyzed in consideration of signal integrity (SI). Based on the physical design, we obtained the interconnect length in detail. The interconnect energy and delay of the silicon interposer and on-chip interconnect were modeled through a SPICE simulation. We analyzed the accurate effects of interconnect reduction caused by PIM. For overall system performance and efficiency analysis, a cycle-level architectural simulation was conducted. We successfully evaluated and analyzed the system performance for memory-intensive applications. As a result, the proposed PIM-HBM achieves 53% and 10.4% improvement on average in computing performance and energy efficiency compared to the conventional graphic processing unit of high bandwidth memory (GPU-HBM).

In this paper, we, for the first time, designed and analyzed differential high-speed serial links of the silicon interposer including differential through-silicon-via (TSV) channels for a high-bandwidth memory (HBM) graphic module. The meshed ground plane and various parameters were considered in designing the silicon interposer. In addition, superior designs were proposed to improve signal integrity (SI) for the differential channels in the redistribution layer, TSVs, and the meshed ground. SI of the silicon interposer was successfully analyzed, and the corresponding results were verified based on a full 3-D electromagnetic solver and circuit simulations. A number of RLGC parameters were extracted and calculated, then adopted to verify the simulation results. The simulation results for the differential characteristic impedance and insertion loss were compared with those of the equivalent circuit. A mixed-mode conversion matrix was utilized to analyze differential-mode transmission. Moreover, a model for differential TSV channels was proposed to precisely analyze the electrical characteristics. The eye-diagram simulation was conducted to evaluate SI of the proposed designs in terms of an eye-opening voltage and timing jitter. The eye-opening voltage of the proposed design was 0.594 V, which is 45.69% of a peak-to-peak voltage of the assumed peripheral component interconnect (PCI)-express 4.0 interfaces. It is expected that the analysis and design methodologies of differential high-speed serial links for a silicon interposer could be widely adopted in the semiconductor industry.

In this article, we propose a near field analytical model of an electromagnetic interference reduction method using an nth harmonic frequency shielding coil with efficiency enhancement in a loosely coupled automotive wireless power transfer system. In general, in the loosely coupled automotive wireless power transfer system, the power transfer efficiency is relatively lower than a tightly coupled wireless power transfer system due to the low coupling. In addition, the electromagnetic interference at the nth harmonic frequency from the power source can interfere with nearby electronic devices. To reduce electromagnetic interference level and enhance efficiency, we proposed a shielding coil between a transmitter and a receiver coil. By using a near field analytical model of the magnetic field intensity and efficiency equations, we analyze based on the equations and obtain a proper value of the resonant frequency of the shielding coil. Therefore, we can achieve low levels of electromagnetic interference at the specific nth harmonic frequency and higher value of the power transfer efficiency in the loosely coupled automotive wireless power transfer system.

In this paper, we measured and analyzed glass interposer power distribution network (PDN) resonance effects on a high-speed through glass via (TGV) channel for the first time. To verify the glass interposer PDN resonance effects on the TGV channel, glass interposer test vehicles were fabricated. With these test vehicles, glass interposer PDN impedance, channel loss, far-end crosstalk, and eye diagram are measured. Based on these measurements, glass interposer PDN resonance effects on the signal integrity of the high-speed TGV channel are analyzed. Due to low loss of the glass substrate, sharp high PDN impedance peaks are generated at the resonance frequencies. High PDN impedance peaks at the PDN resonance frequencies, which affect return current of the TGV channel, increase channel loss, crosstalks, and PDN noise coupling in the frequency domain and degrade eye diagram in the time domain. To suppress these glass interposer PDN resonance effects, a ground shielded-TGV scheme is proposed. The proposed ground shielded-TGV scheme includes two ground TGVs 200 μm away from the signal TGV considering the design rules and includes package ground underneath the glass interposer. Effectiveness of the suggested grounding scheme on the resonance effects suppression is verified with three-dimensional electromagnetic simulation. The proposed shielded-TGV design successfully suppressed the glass interposer PDN resonance effects that results in the suppression of insertion loss, shielding of the crosstalk, and improvement of the eye diagram of the high-speed TGV channel.