In the realm of electronics, the performance of Silicon Trigate Rectangular Nanowires (Si-TRNW) and the structural characteristics of orientation using tight-binding models have been analyzed. The fast algorithm based on the tight-binding model for Trigate Silicon nanowires yielded a remarkable I_ON/I_OFF ratio of 1.49 × 10¹⁰ and leakage current (I_Leak or I_OFF) of 3.7 × 10⁻¹⁷μA. Furthermore, a maximum conduction band energy level (E_cmax) of −0.003 eV and a Subthreshold Slope (SS) of 120 mV has been obtained for a channel length of 15 nm. At an energy level of 3 eV, a high Transmission coefficient, T(ε), of 4 has been attained using the E-k dispersion method. This analysis also involved the calculation of three ∆ valleys pertinent to the channel’s effectiveness in orientation, with proximity nearer to 1 m₀. The Schrodinger-Poisson equation has been analyzed with the Ballistic transport along the [001] z-direction in channel potential. A comparative assessment has been also performed between the lateral dimensions of rectangular nanowires with equal energy levels, utilizing both the tight-binding model and Density Functional Theory (DFT) techniques. In some high-frequency applications, a high transmission coefficient is beneficial to maximize the amount of energy or information that gets transmitted. Reducing leakage current would offer a technological pathway for performance improvement of high-frequency applications. The high ON-current (I_ON) has been obtained through the DFT approach between source and drain terminals is particularly desirable for applications demanding for fast switching speeds and high-performance computing. The strengths of both methods in hybrid approaches is a common strategy to achieve simulations that are both accurate and efficient. Notably, the nanowires subjected to hydrostatic strain, exhibiting enhanced mobility and exceptional electrostatic integrity, emerged as pivotal components for forthcoming technology nodes. This research augments the potential feasibility of strain-based Si nanowires, even at the 3 nm scale, in subsequent technological advancements.

The advancements in semiconductor technology greatly impact the growth of hybrid VLSI devices and components. The nanometer technology has been possibly executed due to the enhancement of the scaling factor of the MOSFETs. Since the MOSFETs play a vital role in building dense devices, it also has several research insights with various semiconductor materials with high-к dielectrics. The high-к dielectric material in place of the conventional oxide layer in the MOSFET design results in improved performance by reducing the Short Channel Effects (SCEs). In this research work, an analytical model of the lightly doped Cylindrical Surrounding Double-Gate (CSDG) MOSFET has been realized. The capacitive modeling has been done for this cylindrical structure. This modeling has been analyzed for all operating regions of the transistors, capacitance estimation, and electrical field dependence on the capacitance. The results have been compared with the previous research and tabulated. It has been observed that the transconductance ( $\text{G}_{\mathrm {m}}$ ) values have been raised to 0.0106 $S/\mu m$ from 0.000645 $S/\mu m$ with the inclusion of 2D electron gas in the core of CSDG MOSFET. This novel model occupies less area on the board, and routing is more accessible than the conventional DG MOSFET design. The overall results have been following the agreement in terms of accuracy, area tradeoff, and high speed, making the novel model suitable for high-frequency/RF applications.

The structural improvement and rapid production of InP, InAs (III-V, binary), and AlGaAs (III-V, ternary) compound semiconductor materials have invariably enabled its utilization in typical high-speed device applications. Using the electronic simulator tool, the ON- and OFF-state drain current (ION/IOFF) performance of InP/InAs/AlGaAs High Electron Mobility Transistors (HEMTs) with Lanthanum Oxide (La2O3) as a dielectric material has been analyzed and thereafter a design of cylindrical surrounding gate MOSFET has been planned with this novel heterostructures. The InAs spacer (primary) layer is placed as per requirement below the source and drains the terminal to improve mobility. A heavily doped AlGaAs channel layer is employed beneath the primary layer, followed by the required layers. The given device gate length of LG = 5 nm, source-drain device length LSD = 0.15 μm and VGS = VDS = 1 V of InP/InAs/Al0.53Ga0.47As HEMT having Equivalent Oxide Thickness (EOT) of La2O3 as 2 nm (gate dielectric oxide), the measured values of maximum drain current (ID, max), transconductance (Gm), Charge carrier density (ρ), and leakage current (Ileak) are 10 mA/μm, 12 mS/μm, 1.5 C/cm3, and 0.03 μA/μm respectively. The electrostatic potential (φ) and electric field (E) are 2.58 V and -47.12 V/μm are obtained when VDS= 1 V. This proposed design enhances the heterostructures immune to all the Short Channel Effects (SCEs) in the RF range that can be used in low power circuits design. Furthermore, the rotational cylindrical structure paves the way for a lesser board area to be occupied to reduce heat generation.

The heterostructures are suitable for developing high-performance electronic and optoelectronic devices. In this work, a significant interest in the design and analysis of compound semiconductor Aluminium Gallium Arsenide (AlGaAs) and Gallium Arsenide (GaAs) heterostructures has been realized. These structures are fabricated with alternating layers of GaAs (a direct bandgap material) and AlGaAs (an indirect bandgap material) and have been used to design a range of high-performance devices, including lasers, solar cells, and field-effect transistors. A 30 nm AlGaAs consisting of a middle layer between two GaAs layers with a GaAs substrate has been reported. This work has been carried out at 300 K utilizing a quantum transport and self-consistent method for the proposed AlGaAs/GaAs one-dimensional heterostructure with a gate length of 2 nm and a voltage varying from 0 to 0.1 V. The measured values of doping density (n_d) and electron density (n_e) of AlGaAs/GaAs one-dimensional heterostructure are 8.96 × 10¹¹ cm⁻³ and 2 × 10²⁶ cm⁻³, respectively. The system response to geometric changes in several parameters has been realized. Hence, confined restricted states were computed using wave functions and energies. The GaAs layer on top of quantum well heterostructure interfaces has been used to modulate the wave functions (eigenstates) resulting in pseudo-one dimensional or small-dimension eigenstates. In this work, a comprehensive analysis of 1D AlGaAs/GaAs heterostructure through benchmarking with several homo-structures (various thicknesses) has been performed.

Cylindrical Surrounding Double-Gate (CSDG) MOSFETs have been designed for a suitable CMOS replacement to diminish the power and area tradeoff. With these MOSFETs below 70 nm node for Semiconductor Industry Association (SIA) roadmap, the CMOS technology has excellent immunity to the Short Channel Effects (SCE) and better scalability. To reduce the SCE, the device was analyzed by improving the gate oxide thickness between the gate terminal and channel material and replacing the conventional Silicon dioxide layer with numerous high-. dielectric materials. The gate oxide thickness is scalable so that it should have the same thickness as that of the Equivalent Oxide Thickness (EOT). This kind of novel structure shows improvement in the ON-state current and OFF-state current. The usage of the cylindrical surrounding double-gate and the high-. dielectric in the oxide layer makes the MOSFET with improved stability and controllability. In this paper, the high-. material is chosen in a way that it has been applied in the CSDG environment and the electrical field, electron densities have been analyzed. The semiconductor can exhibit various energy bands at the Fermi level, commonly referred to as valley. These kinds of valley semiconductors, which have several valleys are called multi-valley semiconductors. The current value in valley-1 is 2.41 mA/μm; it also drops to 62.14 % than valley-4, which has 6.38 mA/μm. However, valley-2 and valley-3 have intermediate values. The energy in the sub-band for the operating region of the source has been observed to be 19.12 % to the drain side which has the value of 0.041 eV at the terminal end. This shows the modeled CSDG MOSFET works well with the operating electric field created by the cylindrical capacitors constituted by the two different gate materials surrounding the substrate.