In this paper, a novel architecture of an SRAM-based Physical Unclonable Function (PUF) whose unstable cells are identified and masked by a ``capacitive tilt'' preselection test is proposed. During the preselection test, either one of the cross-coupled inverter nodes is loaded with a digitally controlled capacitance, which can tilt the PUF towards a ``1'' or a ``0''. Any cell which maintains its value during this test is deemed stable. Each capacitor bank is shared between four PUF cells, such that the additional area required is only 20%. This test does not require precision analog voltages, as did previous tests, and can thus be implemented by the user during key enrollment. In a test-chip implementation in TSMC 65nm node, the preselection test identified and disqualified all the cells that were measured as unstable in 18 PUF arrays, of 800 bits each. An overall scheme for PUF stabilization is proposed, composed of two error-reductions steps, comprising Inner and Outer error control blocks. The outer error control is typically a BCH code, which guarantees a required key error rate. The inner error control can either be the proposed tilt test, a BCH code, or another error correction scheme. To maximize the ratio of reliable key bits to physical PUF cells, i.e., the overall PUF code rate, several solutions were analyzed. It is shown that in order to achieve a key error rate of 1E-9, the most efficient construction is a tilt test followed by BCH[184,128,15], with a PUF code rate of 0.49. In addition, the tilt test is more efficient in terms of power, area and execution time than the other inner error correction mechanisms. Therefore, this construction is not only efficient by its overall code rate, but also by its area and its power, and further, it enables a more lightweight BCH implementation for the outer code.

A modified weak SRAM Physical Unclonable Function (PUF) is proposed which is much more reliable than prior-art SRAM PUFs. The proposed PUF was fabricated in TSMC 65nm process. A novel preselection test was run on these PUF arrays and is shown to eliminate all of the unstable cells (20-25%). This PUF can drastically reduce the need for Error Correction Codes (ECC). In addition, the preselection test can be accomplished in one VDD / Temperature corner, which reduces the testing cost of finding unstable bits across many such corners, as is done in the prior art.

Power analysis attacks have become a serious threat to security systems by enabling secret data extraction using side-channel leakage information. Embedded memories, often implemented with 6T SRAM cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel leakage power attacks. To provide resiliency to these types of attacks, we propose a symmetric 8T SRAM cell which incorporates two more transistors than the conventional 6T cell to significantly reduce the correlation between the stored data and the leakage currents. To demonstrate the improved security of the suggested memory array, both cells were implemented in a 65-nm CMOS technology. Simulation results, including Monte Carlo analysis and signal-to-noise ratio comparison, illustrate the resiliency of the 8T cell to leakage power attacks.

Fault-based attacks against cryptographic circuits must be addressed by techniques that are different from approaches designed for random transient faults. We systematically investigate robust error-detecting codes that specifically target malicious attacks and guarantee minimal bounds on detection probability. Our study is based on FPGA-supported fault-injection campaigns on the circuit implementation of a recent lightweight block cipher and its sub-modules. We quantify the detection capabilities of different robust and non-robust codes with respect to both random faults and malicious attacks, as well as the required overheads. For the first time, we report performance of a novel punctured cubic code on actual cryptographic circuitry. Experimental results show that robust codes with a certain number of redundant bits have better detection properties in security context and higher predictability than their conventional linear counterparts.

Leakage of information through the power supply current has become a major factor in logic design. In this paper, a low cost and simple to employ design methodology dubbed pseudoasynchronous is presented. This design style combines the security advantages of asynchronous circuits with the ease of synchronous circuit design. Randomization and data-dependencies (DD) are utilized to hide information leakage from the current dissipation, and hence making the critical synchronization of power supply current traces hard to do. In addition, randomization and DD are utilized for both time-domain hiding of information leakage during the active region (dynamic currents) and for amplitude-domain hiding of information leakage during the static-region (leakage currents). The main advantages of this new approach are low area cost, reduced signal, and increased noise. Circuit-level analyses show that it is harder to exploit the information leakage from internal signals of the proposed design than from CMOS-based synchronous designs or other forms of time-domain hiding countermeasures.