In this paper, a novel architecture of an SRAM-based Physical Unclonable Function (PUF) whose unstable cells are identified and masked by a ``capacitive tilt'' preselection test is proposed. During the preselection test, either one of the cross-coupled inverter nodes is loaded with a digitally controlled capacitance, which can tilt the PUF towards a ``1'' or a ``0''. Any cell which maintains its value during this test is deemed stable. Each capacitor bank is shared between four PUF cells, such that the additional area required is only 20%. This test does not require precision analog voltages, as did previous tests, and can thus be implemented by the user during key enrollment. In a test-chip implementation in TSMC 65nm node, the preselection test identified and disqualified all the cells that were measured as unstable in 18 PUF arrays, of 800 bits each. An overall scheme for PUF stabilization is proposed, composed of two error-reductions steps, comprising Inner and Outer error control blocks. The outer error control is typically a BCH code, which guarantees a required key error rate. The inner error control can either be the proposed tilt test, a BCH code, or another error correction scheme. To maximize the ratio of reliable key bits to physical PUF cells, i.e., the overall PUF code rate, several solutions were analyzed. It is shown that in order to achieve a key error rate of 1E-9, the most efficient construction is a tilt test followed by BCH[184,128,15], with a PUF code rate of 0.49. In addition, the tilt test is more efficient in terms of power, area and execution time than the other inner error correction mechanisms. Therefore, this construction is not only efficient by its overall code rate, but also by its area and its power, and further, it enables a more lightweight BCH implementation for the outer code.

A modified weak SRAM Physical Unclonable Function (PUF) is proposed which is much more reliable than prior-art SRAM PUFs. The proposed PUF was fabricated in TSMC 65nm process. A novel preselection test was run on these PUF arrays and is shown to eliminate all of the unstable cells (20-25%). This PUF can drastically reduce the need for Error Correction Codes (ECC). In addition, the preselection test can be accomplished in one VDD / Temperature corner, which reduces the testing cost of finding unstable bits across many such corners, as is done in the prior art.

Compact integrated thermal sensors are utilized to measure hot / cold spots in CPU cores in multiple locations and are important for the power/performance of the chip. Bipolar junction transistors (BJT) are the industry standard for temperature sensing elements because of their predictable physics. This paper reports on one of the smallest PNP BJT bandgap based thermal sensors to date. Miniaturization was achieved by using switched capacitor circuits with very small capacitors as opposed to the standard resistor-based bandgaps. Digitally controlled trims enable either a higher resolution or a nearly linear response to temperature. This ultra-miniature 0.003 mm ² , PNP thermal- based sensor is fabricated in TSMC 65nm. It achieves a measured total ±3σ error of ±1.35°C with a resolution of 65mK and a 4.1ms conversion time. The sensor is optimized for dense CPU thermal mapping.

Nearly all integrated circuits contain power and thermal management circuits. These two functions are intimately connected and help improve the power performance of the system. In recent generation computers, the functionality and complexity of the thermal sensing and management circuits have accelerated in order to improve the performance. Integrated thermal sensors are utilized to monitor the peak temperatures of the CPU’s to ensure that they do not exceed the reliability limits. There are many hot-spots on the CPU which have to be monitored, and these locations are not necessarily obvious during the design stage. As a result, it is required that there be multiple sensors on the CPU to enable accurate coverage. Thermal sensors are needed for cold-spot monitoring as well, in order to determine the required Vdd level during low voltage, low power modes. The sensors are also used for fan regulation and power estimation. There can be many tens of sensors in a product, which require them to be small and low power. A variety of mechanisms have been utilized to form the sensing element. These include the parasitic PNP transistor, MOS transistors, resistors, as well as the thermal diffusivity of Si. In the past ten years, a trend towards miniaturization of thermal sensors has occurred. This review paper surveys the recent miniaturized integrated sensors which have been reported in the literature. The design tradeoffs for the CPU application are discussed, as well as the relative advantages of the different sensing mechanisms and their performances.

Thermal sensing is a key power management feature in microprocessor products and other integrated circuits. There can be as many as 40 sensors on a chip. Thus, it is important for these sensors to have a highly compact area, as well as low energy. In this paper, we report a novel resistor-based thermal sensor with an area of 0.01 mm2 in 65-nm process, an energy consumption of 0.9 nJ/conversion, and a conversion speed of 80 μs. This sensor is one of the smallest, fastest, and lowest energy sensors reported which utilize resistors as the sensing element, making it optimal for CPU applications. The sensor has a competitive resolution figure of merit of 0.02 nJ·K2, as well as a relative inaccuracy of 1.4 °C, which easily meets the accuracy requirements of these applications. The circuit architecture is based on the measurement of an RC time constant using a novel amplifier/comparator circuit, along with a dynamic bias for power savings.

Temperature monitoring and regulation is a critical power/performance feature in microprocessors. Due to the multiplicity of hotspots, a large number of on-die sensors are utilized. This requires them to be highly compact, low energy and fast. A miniaturized current controlled oscillator (CCO) sensor is described for this application. It has an area of only 700 $\mu \text{m}^{2}$ in the 16-nm FinFET process, with an energy consumption of 0.25 nJ in a 6.9- $\mu \text{s}$ conversion. The inaccuracy is within ±1.5 °C peak-to-peak (p-p) over a 130 °C range, at a resolution of 0.32 °C. These characteristics make the circuit attractive for high-density thermal sensing.