The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

This work focuses on the separation and quantification of fixed bulk oxide charge, fixed charge at the dielectric–semiconductor interface and interface state charge components in the Pt/Al₂O₃/In_0.53Ga_0.47As metal-oxide-semiconductor (MOS) system. The availability of atomic layer deposited Al₂O₃ dielectrics over n- and p-type In_0.53Ga_0.47As with a range of well-controlled thickness values opens up an experimental route for the determination of the interface state density (D_it) independently of the total fixed oxide charge using capacitance–voltage measurements taken at 1 MHz and −50°C. Low temperature forming gas annealing (350°C) significantly reduces the amount of fixed charge. The interface fixed charge is reduced from ∼ −8.5 × 10₁₂ cm₋₂ preanneal to ∼ −7.4 × 10₁₁ cm₋₂ postanneal and the bulk oxide charge is reduced from ∼1.4 × 10₁₉ cm₋₃ preanneal to ∼5 × 10₁₈ cm₋₃ postanneal. The forming gas anneal also has a significant effect on the interface state charge, reducing its density from 1.3 × 10₁₃cm₋₂ preanneal to 4 × 10₁₂ cm₋₂ postanneal.

An unpinned interface between an layer deposited by atomic layer deposition (ALD) and a chemically treated is demonstrated. The starting surface was prepared by wet etching with followed by a thermal desorption of residual As at immediately before ALD. Analysis of temperature-dependent capacitance–voltage measurements suggests that the Fermi level can sweep through the bandgap of , attaining true accumulation and inversion despite the presence of In oxide and In hydroxide at the interface. This is in contrast to the situation for residual As-related interfacial species, which have been reported to pin the Fermi level at oxide/III–V interfaces.