As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed.

Small delay defects (SDD) based test escapes are caused by the nature of transition delay fault (TDF) ATPG, which propagates the fault effect along the shorter path in the interest of run time. However, owing to the benefits of a lesser pattern count and complexity, TDF ATPG is the most feasible option for delay testing. Faster than at-speed testing enhances the likelihood of detecting SDD. To generate the optimal test option and prevent over or under-testing the circuit, it is necessary to select the appropriate test clock period. The recently introducedWeighted slack percentage (WeSPer) metric is used in this article to identify the best SDD test option. The method’s benefit is combined with the proper selection of the optimal clock frequency to test the SDD. This article proposes an optimal test clock period selection method by considering the size of the smallest possible delay defect size that can fail the circuit during at-speed operation and the fault’s propagation delay. The proposed method is applied to the set of ISCAS89 and ITC99 benchmark circuits to evaluate its effectiveness.