Sivanantham Sathasivam

Dr. Sivanantham Sathasivam

School of Electronics Engineering, Vellore Institute of Technology, Vellore, Vellore, India
orcid

Research Focus & Metrics

Academic Career Length

16Years (2011-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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2 February 2016 in Far East Journal of Electronics and Communications
Verified
Journal Article
Closed access
SSSivanantham Sathasivam
Sivanantham Sathasivam
NPN. Nitin Paul
N. Nitin Paul
RIR. Suraj Iyer
R. Suraj Iyer

1 September 2014 in Integration
Verified
Journal Article
Closed access
SSSivanantham Sathasivam
Sivanantham Sathasivam
MPM. Padmavathy
M. Padmavathy
GGGanga Gopakumar
Ganga Gopakumar
PMPartha Sharathi Mallick
Partha Sharathi Mallick
JPJ. Raja Paul Perinbam
J. Raja Paul Perinbam

10 September 2022 in Applied Sciences
Verified
Journal Article
Open access
PDF file
PMPRATHIBA MUTHUKRISHNAN
PRATHIBA MUTHUKRISHNAN
SSSivanantham Sathasivam
Sivanantham Sathasivam
As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed.

1 October 2018 in Computers and Electrical Engineering
Verified
Journal Article
Closed access
TKThilagavathi Kothandabani
Thilagavathi Kothandabani
SSSivanantham Sathasivam
Sivanantham Sathasivam

1 November 2015
Verified
Conference Paper
Closed access
MAManjunath
Manjunath
VHVenama Harikiran
Venama Harikiran
KMKopparapu Manikanta
Kopparapu Manikanta
SSSivanantham Sathasivam
Sivanantham Sathasivam
KSK Sivasankaran
K Sivasankaran
The Modified Booth multiplier is attractive to many multimedia and digital signal processing systems. This paper presents the design of 16*16 Modified Booth multiplier. The multipliers such as Braun array multiplier and Array multiplier are used for unsigned multiplication. This paper focusing on design of Modified Booth Multiplier which performs both signed and unsigned multiplication. Here used Carry Select Adder it increases the speed of multiplier operation. Booth encoder multiplier with Carry select Adder utilizes the minimum hardware, reduced chip area, low power dissipation and reduced the cost of the system.

1 May 2014 in Computers and Electrical Engineering
Verified
Journal Article
Closed access
SSSivanantham Sathasivam
Sivanantham Sathasivam
PMPartha Sharathi Mallick
Partha Sharathi Mallick
JPJ. Raja Paul Perinbam
J. Raja Paul Perinbam