The convergence of HPC and AI has brought about a diversification of precision, posing significant hardware implementation challenges. This paper aims to address this issue by presenting a low-cost floating-point (FP) fused multiply-add (FMA) unit that is capable of supporting a wide range of FP formats. For the fewer-than-64-bit formats, this innovative FMA unit performs standard or mixed-precision operations fully pipelined in parallel for SP, TF32, BF16, and HP formats. For the 64-bit DP format, the FMA and ADD operations, whether independent or data-related, can be organized into package operations that are executed in two consecutive cycles to eliminate pipeline stall and then improve performance. The proposed FMA unit utilizes iteration and hardware vectorization methods to balance between cost and performance. Compared to a conventional DP FMA unit, the proposed design not only supports a wider range of FP formats and functions but also achieves higher performance with less cost. It can improve performance up to 1.5x more than the dual-mode FMA unit when performing HPC-AI applications.

The reality of the ray tracing technology that leads to its rendering effect is becoming increasingly apparent in computer vision and industrial applications. However, designing efficient ray tracing hardware is challenging due to memory access issues, divergent branches, and daunting computation intensity. This article presents a novel architecture, a RT engine (Ray Tracing engine), that accelerates ray tracing. First, we set up multiple stacks to store information for each ray so that the RT engine can process many rays parallel in the system. The information in these stacks can effectively improve the performance of the system. Second, we choose the three-phase break method during the triangle intersection test, which can make the loop break earlier. Third, the reciprocal unit adopts the approximation method, which combines Parabolic Synthesis and Second-Degree interpolation. Combined with these strategies, we implement our system at RTL level with agile chip development. Simulation and experimental results show that our architecture achieves a performance per area which is 2.4 × greater than the best reported results for ray tracing on dedicated hardware.

Recent strides in hardware-accelerated ray tracing have propelled algorithms once deemed suitable only for offline rendering, like Monte Carlo path tracing, into interactive frame rates. While path tracing has been regarded as a practical utility in animating scenes for the film industry, achieving visually noise-free imagery often mandates thousands of samples per pixel and considerable computation time. Regrettably, this poses a difficulty for video games and virtual reality applications, which demand high frame rates and resolutions, thereby constraining the computational overhead of path tracing. Two extant approaches, in-process sampling, and post-processing reconstruction methods, i.e., denoising and upsampling, address this challenge. The giant evolution of deep learning technology has emerged as pivotal in path tracing processing. We explore and advance Monte Carlo path tracing technology based on deep learning. Moreover, we illustrate the merits and demerits of diverse designs and technologies, propose potential future development trends, and aim at providing researchers with a comprehensive understanding of the cutting-edge in deep learning-driven Monte Carlo path tracing.

Dividing a single System-on-Chip (SoC) into multiple chiplets and integrating them via an interposer can achieve an optimal balance between continuous transistor integration and monetary cost. However, potential deadlock may arise between the chiplets and the interposer. This deadlock can be avoided by applying turn restriction or injection control on the boundary routers, at the cost of additional latency and suboptimal performance. Compared to deadlock avoidance, deadlock recovery exerts less impact on network performance. Nevertheless, accurate and timely deadlock detection, along with efficient deadlock recovery, continues to pose significant challenges. Additionally, modularity is a specific concern, which involves integrating chiplets of various functions, sizes, manufacturing processes, and so on. Minimizing the negative impact of deadlock resolution while maximizing modularity is crucial for achieving the benefit of chiplets. This article proposes a modular deadlock detection strategy, Up-Down, which monitors both the upward and downward directions of vertical channels, facilitating information exchange through the congestion-sense network. When a pair of blocked upward and downward vertical channels is detected simultaneously, it is considered that an inter-chiplet deadlock has occurred. This significantly enhances the accuracy of deadlock detection by two orders of magnitude compared to time-out deadlock detection. Furthermore, this article introduces Steered Bubble, a low-cost deadlock recovery algorithm. It does so by injecting bubbles into potential deadlock cycles identified by Up-Down. These bubbles follow preset paths, ensuring efficient deadlock recovery. Experimental results indicate that the Steered Bubble results in an average performance enhancement of 1% to 10% during full-system simulations, with an area overhead of less than 2%.