Stride prediction is a nonignorable part of value prediction. Most hybrid predictors cannot eliminate this pattern. Existing stride predictors can handle the regular stride pattern, but it is hard to fit well with the interval stride pattern. To deal with it, we introduce the notion of Stride Equality Prediction (SEP), which predicts the stride feature of the current instruction is equal to that of the last committed same instruction. SEP can deal well with interval-style stride patterns, which always perform a constant stride during an interval, although there may be different endpoints and strides in different intervals. SEP predicts the value of stride equality instructions from the last committed occurrence of the same instruction and the number of the same instruction in the instruction window. Evaluation results show that SEP is effective in stride value prediction. It outperforms the Enhanced Stride predictor for 5.3% and state-of-art computational predictor Context-based Computational Value TAGE (CBC-VTAGE) for 1.5% on average. Moreover, by applying the SEP update condition, CBC-VTAGE can obtain performance gain without extra cost.

The reality of the ray tracing technology that leads to its rendering effect is becoming increasingly apparent in computer vision and industrial applications. However, designing efficient ray tracing hardware is challenging due to memory access issues, divergent branches, and daunting computation intensity. This article presents a novel architecture, a RT engine (Ray Tracing engine), that accelerates ray tracing. First, we set up multiple stacks to store information for each ray so that the RT engine can process many rays parallel in the system. The information in these stacks can effectively improve the performance of the system. Second, we choose the three-phase break method during the triangle intersection test, which can make the loop break earlier. Third, the reciprocal unit adopts the approximation method, which combines Parabolic Synthesis and Second-Degree interpolation. Combined with these strategies, we implement our system at RTL level with agile chip development. Simulation and experimental results show that our architecture achieves a performance per area which is 2.4 × greater than the best reported results for ray tracing on dedicated hardware.

Value prediction is a microarchitectural technique that enhances processor performance by speculatively breaking true data dependencies. It has demonstrated improved performance in both single-threaded and multi-threaded workloads, rendering it an appealing microarchitectural approach. While high-performance value predictors can achieve impressive accuracy, they may also incur significant costs in terms of area, power consumption, and complexity. Therefore, there is a demand for lightweight value prediction techniques capable of striking a favorable balance between performance and overhead. However, designing value predictors with superior performance using limited resources presents an urgent challenge. Consequently, this work proposes a design space exploration framework for the state-of-the-art EVES value predictor, aiming to efficiently configure the design parameters of the value predictor within constrained RAM resources. Additionally, the article evaluates the performance of the explored value predictor across a wide range of workloads. The explored value predictors exhibit high efficiency across RAM sizes ranging from 2KB to 16KB while maintaining acceptable computational complexity. Furthermore, the results indicate that the explored value predictor achieves optimal efficiency under the 2KB constraint, with the highest acceleration-to-cost ratio reaching 4.02%/KB.