A 24-28-GHz two-stage GaN Doherty power amplifier (PA) is designed and characterized. At millimeter-wave (mm-wave) frequencies, the low output impedance of the auxiliary transistor loads the Doherty combining network, which lowers the power added efficiency (PAE) in back-off. In this design, a small periphery auxiliary transistor is used to increase the output impedance of the auxiliary transistor. The periphery ratio of the auxiliary and the main transistors is 77%. Even though, compared to symmetric Doherty PAs, the load modulation of the main transistor is reduced, this amplifier still achieves 32% and 23% PAE at 6 and 9-dB output power back-off, respectively. Attributing to the small auxiliary transistor, the amplifier obtains a small signal gain of 19 dB. The maximum output power of the amplifier is 4 W with a peak PAE of 42%.

In this letter, we report two high-power gallium nitride (GaN) power amplifiers (PAs) in the Satcom $E$ -band (71–86 GHz) with an output power of 2.6 and 4 W, designed by incorporating an ultralow-loss on-chip integrated power combiner. The first one is a three-stage four-way combining (unit) PA, and the second one is an eight-way combining balanced PA. The unit PA produces a saturated output power ( $P_\textsc{SAT}$ ) of 34.2 dBm (2.6 W), a peak power-added-efficiency (PAE) of 22%, and an associated power gain of 16.2 dB at 74 GHz. This performance was partly made possible by the design and optimization of the low-loss integrated power combiner, which minimized the losses in the matching networks. In addition, the balanced PA produces a $P_\textsc{SAT}$ of 36 dBm (4 W), $P_\text{1 dB}$ of 35.6 dBm (3.63 W), with an associated PAE of 15.3% at 80 GHz. To the best of the authors’ knowledge, this is the highest output power (4 W) and the highest PAE (22%) for a PA $>$ 2.5 W reported in any of the III–V technologies at $E$ -band.

This work presents a packaging technique for Monolithic Microwave Integrated Circuits (MMIC) demonstrated in a fully integrated receiver (Rx) module at D-band (110 - 170 GHz). The solution consists of a MMIC-to-waveguide transition realized using an on-chip probe mounted in the E-plane of a split-block waveguide module. An Artificial Magnetic Conductor (AMC) structure is implemented to suppress cavity modes and achieve better coupling from the waveguide to the probe. The transition's performance is experimentally verified using a back-to-back test chip and measurement results show that the proposed packaging solution achieves a low insertion loss of only 0.7 dB and covers a very wide frequency range extending from 105 to 175 GHz. The proposed transition is also integrated with an in-phase/quadrature-phase (I/Q) Rx on the same chip. The Rx is realized in a 250-nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology and consists of a low noise amplifier (LNA), an I/Q mixer and a frequency tripler. Measurement results show that the Rx module achieves an average conversion gain of 23 dB across the frequency range of 110-145 GHz and has an average noise figure (NF) of 10.6 dB. The Rx MMIC has a dc power consumption of 440 mW and occupies an area of $1.6 \times 1.6\;\text{mm}^2$ . This work addresses one of the main challenges in systems operating above 100 GHz and presents a fully integrated packaging solution that suits large integrated circuits and does not require any galvanic contacts nor impose any limitations on MMIC dimensions.

A D-band frequency quadrupler consisting of two cascaded push-push doublers is designed and manufactured in a 0.25 μm InP DHBT technology. Each doubler has a Marchand balun implemented by broadside-coupled transmission lines, folded in a rectangular shape. The second balun, operating at a half of output frequency, is located inside of the first one for minimizing the chip size. The frequency quadrupler with a dc power consumption of 47 mW has a maximum conversion gain of 2 dB, and exhibits 12 to 25 dBc rejection ratio of the undesired first to fifth harmonics in the frequency range from 110 to 130 GHz. The quadrupler demonstrates a power efficiency of 10%, which is the highest among published quadruplers, as well as the highest conversion gain and an output power of 5 ~ 7 dBm without using power amplifiers. The chip size is 0.77 mm ² . By switching a cascode transistor, the quadrupler can also be used as an on-off keying modulator.

A 23 GHz balanced Hartley VCO is designed and manufactured in 0.13 mum COMS technology. In this VCO design, a pair of coupled inductors are employed to make the whole circuit compact. Its size is only 0.17 mm ² . Very low phase noise, -108 dBc/Hz at 1 MHz offset frequency, is measured and a wide tuning range of 13% is achieved. In addition, the VCO consumes only 5.7 mW dc power at 0.79 V supply voltage ^* .

A high data rate RF-DAC and a power detector (PD) are designed and fabricated in a 250 nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A communication link using the Tx-Rx over polymer microwave fiber (PMF) is measured. The link consists of a pulse amplitude modulation (PAM) modulator and a PD as a demodulator, as well as a one-meter-long dielectric waveguide. The working frequency range of the complete link is verified to be 110–150 GHz. The peak output power of the PAM modulator is 5 dBm, and it has a −3 dB bandwidth of 43 GHz. The PD consists of a parallel connected common emitter configured transistor and a common base configured transistor to suppress the odd-order harmonics at the PD’s output, as well as a stacked transistor to amplify the output signal. Tx and Rx chips, including pads, occupy a total area of only 0.83 mm². The PMF link can support a PAM-4 signal with 22 Gbps data transmission, and a PAM-2 signal with 30 Gbps data transmission, with a bit error rate (BER) of <10−12, with demodulation performed in real time. Furthermore, the energy efficiency for the link (Tx + Rx) is 4.1 pJ/bit, using digital data input and receiving PAM-2 output (5.6 pJ/bit for PAM-4).