The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field ($E_{eff}$) on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be $E_{eff}^{-1.8}$ and $E_{eff}^{-2.4}$, respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of $E_{eff}$ in controlling the value of channel mobility in 4H-SiC MOSFETs.

In this work, p-channel 4H-SiC MOSFETs were fabricated and analyzed at high temperature. It is demonstrated that nitridation of the gate oxide enables enhancement mode operation in these devices. Nitrogen incorporation at the 4H-SiC/SiO₂ interface by nitric oxide annealing reduces the interface trap density energetically located in the lower half of the 4H-SiC bandgap, resulting in viable high temperature p-channel devices. In the 27–300 °C temperature range, the threshold voltage decreases with increasing temperature, consistent with the reduction of occupied interface traps at higher temperatures. The hole channel mobility is weakly temperature dependent under strong inversion conditions. Hall measurements support that above the threshold voltage, the mobility is limited by surface roughness scattering. In weaker inversion, the channel conductivity is limited by interface hole trapping and Coulomb scattering. In addition, high temperature bias stress measurements confirm a temperature activated hole trapping under negative gate bias, which requires further investigations.

We report an N2 based annealing treatment to passivate interface traps (Dit) in n- and p-type 4H-SiC. The process has the potential to replace the commonly used hazardous and expensive gas nitric oxide (NO). N2 postoxidation annealing reduces Dit in both the upper and lower halves of the 4H-SiC bandgap, with a greater impact at the valence band edge. N2 annealing at 1500 °C is observed to be more effective in passivating traps and positive fixed charges than NO annealing for p-type devices, whereas for n-type devices, the opposite is true. The breakdown voltages for these devices are found to be lower than that of NO annealed devices. X-ray photoelectron spectroscopy has been performed to estimate the nitrogen areal density at the interface. Dit is measured as a function of nitrogen areal densities in the near interfacial regions for the different processes. Theoretical analysis through density functional theory is consistent with the measured Dit profiles by showing the generation of additional states near the valence band edge due to increased nitrogen concentration. In addition to reporting the effect of N2 annealing on both n- and p-type 4H-SiC, this work correlates the nitrogen areal densities at the interface to the Dit and explains the difference in Dit characteristics with nitrogen areal density between n- and p-type interfaces.

Recently, a method to extract temperature coefficients of impact ionization (II) from the linear and quadratic temperature coefficients of avalanche voltage was successfully applied for 4H-SiC devices. We apply the same method here to Silicon by first providing new data for linear and quadratic temperature coefficients of avalanche voltages and using the method to derive new temperature coefficients for four different models of II coefficients.

Gated Hall measurements are conducted to calculate interface trap density of a nitric oxide (NO) annealed 4H silicon carbide (4H-SiC) MOSFET. The free carriers are measured using split CV method. Application of body bias confirms that the total trap quantity does not change at the interface when changing the electric field through body bias for a given device. The effect of positive gate stress on Hall mobility is also studied. A stress voltage of +36 V is applied for different stress times (0, 10, 30, 100, and 300 sec). With the increased stress time, the Hall mobility value drops at low gate voltages, while at higher gate voltages they merge. Higher stress creates more interface traps that in turn increase Coulomb scattering which lowers mobility at low gate voltages. The effect of gate stress on Hall mobility provides accurate insight of the channel behavior due to interface traps at 4H-SiC / SiO₂ interface.