This work demonstrates the advantage of carrying out silicon ion (Si+) implantation at high temperatures for forming controlled heavily doped regions in gallium oxide. Room temperature (RT, 25 °C) and high temperature (HT, 600 °C) Si implants were carried out into MBE grown (010) β-Ga2O3 films to form ∼350 nm deep Si-doped layers with average concentrations up to ∼1.2 × 1020 cm−3. For such high concentrations, the RT sample was too resistive for measurement, but the HT samples had 82.1% Si dopant activation efficiency with a high sheet electron concentration of 3.3 × 1015 cm−2 and an excellent mobility of 92.8 cm2/V·s at room temperature. X-ray diffraction measurements indicate that HT implantation prevents the formation of other Ga2O3 phases and results in reduced structural defects and lattice damage. These results are highly encouraging for achieving ultra-low resistance heavily doped Ga2O3 layers using ion implantation.

In this work, a simple method based on low-temperature annealing in air is developed for effective chemical doping in MoS₂. The threshold voltage of multilayer MoS₂ FET can be effectively tuned from depletion mode (Vth = ¬1.8 V) to enhancement mode (Vth = 1.1 V) by annealing in air at 150 °C.

Silicon carbide (4H) based metal–oxide–semiconductor field-effect transistors provide capabilities in high power and high temperature inaccessible to silicon. However, the performance of thermally grown oxide-based devices remains limited by oxide/semiconductor interface defects. This research employs deposited dielectrics, Al₂O₃, rather than thermal oxidation. Investigation of various pre-deposition processes reveals different degrees of improvements in the electronic properties. An optimum structure employs the preparation of a nitrided surface via NO annealing, a process known to passivate surface defects, a hydrogen exposure, followed by Al₂O₃ deposition. Inversion layer field-effect mobilities as high as 52 cm²/V s are reported in the optimum structures. Capacitance–voltage measurements and field-effect mobility characteristics indicate a trapping limited conductivity in Al₂O₃/4H-SiC inversion channels similar to SiO₂/4H-SiC. Leakage currents and interface breakdown are also reported for various Al₂O₃/4H-SiC MOS structures.

The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field ($E_{eff}$) on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be $E_{eff}^{-1.8}$ and $E_{eff}^{-2.4}$, respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of $E_{eff}$ in controlling the value of channel mobility in 4H-SiC MOSFETs.

In this work, p-channel 4H-SiC MOSFETs were fabricated and analyzed at high temperature. It is demonstrated that nitridation of the gate oxide enables enhancement mode operation in these devices. Nitrogen incorporation at the 4H-SiC/SiO₂ interface by nitric oxide annealing reduces the interface trap density energetically located in the lower half of the 4H-SiC bandgap, resulting in viable high temperature p-channel devices. In the 27–300 °C temperature range, the threshold voltage decreases with increasing temperature, consistent with the reduction of occupied interface traps at higher temperatures. The hole channel mobility is weakly temperature dependent under strong inversion conditions. Hall measurements support that above the threshold voltage, the mobility is limited by surface roughness scattering. In weaker inversion, the channel conductivity is limited by interface hole trapping and Coulomb scattering. In addition, high temperature bias stress measurements confirm a temperature activated hole trapping under negative gate bias, which requires further investigations.