An Informed RRT* (IRRT*) algorithm is one of the optimized versions of a Rapidly-exploring Random Trees (RRT) algorithm which finds near-optimal solutions faster than RRT and RRT* algorithms by restricting the search area to an ellipsoidal subset of the state space. However, IRRT* algorithm has the disadvantage of randomness of sampling and a non-real time process, which has a negative impact on the convergence rate and search efficiency in path planning applications. In this paper, we report a hybrid algorithm by combining the Artificial Potential Field Method (APF) with an IRRT* algorithm for mobile robot path planning. By introducing the virtual force field of APF into the search tree expansion stage of the IRRT* algorithm, the guidance of the algorithm increases, which greatly improves the convergence rate and search efficiency of the IRRT* algorithm. The proposed algorithm was validated in simulations and proven to be superior to some other RRT-based algorithms in search time and path length. It also was performed in a real robotic platform, which shows that the proposed algorithm can be well executed in real scenarios.

There are several significant advantages of memristors, such as their nano scale, fast switching speed, power efficiency and compatibility with CMOS technology, as one of the alternatives in the next generation of semiconductor storage devices. D-flip-flops (DFFs) based on the traditional CMOS process have some shortcomings, including a large area, high power, and charge leakage when scaling down. However, memristors offer a new approach to the design of DFFs with improved performance. Two simplified edge-triggered DFFs are proposed to reduce the number of devices via the Memristor-Rationed Logic (MRL) method, which utilizes the characteristic of transmitting signals in the two-stage inversion structure. In addition, two new 4-bit Linear Feedback Shift Registers (LFSRs) are designed and verified using the proposed DFFs. Compared to the partially existing LFSRs, the designed LFSRs reduce the number of devices significantly, decrease the power consumption by 32.7% and 33.3% and shorten the delay time by 34.5% and 30.7% for the NOR and NAND gates, respectively. Finally, the proposed falling-edge-triggered DFF is used to implement the major blocks of the Built-In Self-Test(BIST) circuit, and the simulation results confirm their correctness and feasibility.

Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process.