The early detection of arrhythmia can effectively reduce the risk of serious heart diseases and save time for treatment. Many healthcare devices have been widely used for electrocardiogram (ECG) monitoring. However, most of them can only complete simple two-classes detection and have unacceptable hardware overhead and energy consumption. For achieving accurate and low-power arrhythmia detection, a novel ECG processor application specific integrated circuit (ASIC) is proposed in this paper, which can perform the prediction of five types of cardiac arrhythmias and heart rate monitoring. To realize hardware-efficient R-peak detection, an ECG pre-processing engine based on a first derivative and moving average comparison method is proposed. Efficient arrhythmia detection is realized by the proposed low-power classification engine, which is based on a carefully designed lightweight artificial neural network (ANN) with good prediction accuracy. The hardware reuse strategy is used to implement the hardware logic of ANN, where computations are executed by only one processing unit (PU), which is controlled by a flexible finite state machine (FSM). Also, the weights of ANN are configurable to facilitate model updates. We validate the functionality of the design using real-world ECG data. The proposed ECG processor is implemented using 55 nm CMOS technology, occupying an area of 0.33 mm². This design consumes 12.88 μW at a 100 kHz clock frequency, achieving a classification accuracy of 96.69%. The comparison results with previous work indicate that our design has advantages in detection performance and power consumption, providing a good solution for low-power and low-cost ECG monitoring.

Many electrocardiogram (ECG) processors have been widely used for cardiac monitoring. However, most of them have relatively low energy efficiency, and lack configurability in classification leads number and inference algorithm models. A multi-lead ECG coprocessor is proposed in this paper, which can perform efficient ECG anomaly detection. In order to achieve high sensitivity and positive precision of R-peak detection, a method based on zero-crossing slope adaptive threshold comparison is proposed. Also, a one-dimensional convolutional neural network (1-D CNN) based classification engine with reconfigurable processing elements (PEs) is designed, good energy efficiency is achieved by combining filter level parallelism and output channel parallelism within the PE chains with register level data reuse strategy. To improve configurability, a single instruction multiple data (SIMD) based central controller is adopted, which facilitates ECG classification with configurable number of leads and updatable inference models. The proposed ECG coprocessor is fabricated using 55 nm CMOS technology, supporting classification with an accuracy of over 98%. The test results indicate that the chip consumes 62.2 nJ at 100 MHz, which is lower than most recent works. The energy efficiency reaches 397.1 GOPS/W, achieving an improvement of over 40% compared to the reported ECG processors using CNN models. The comparison results show that this design has advantages in energy overhead and configurability.

Deep convolutional neural networks (CNNs) have shown strong abilities in the application of artificial intelligence. However, due to their extensive amount of computation, traditional processors have low energy efficiency when executing CNN algorithms, which is unacceptable for portable devices with limited hardware cost and battery capacity, so designing a CNN-specific processor is necessary. In this paper, we propose an energy-efficient CNN processor architecture for lightweight devices with a processing elements (PEs) array consisting of 384 PEs. Using the systolic array-based PE array, it realizes parallel operations between filter rows and between channels of output feature maps, supporting the acceleration of 3D convolution and fully connected computation with various parameters by configuring internal instruction registers. The computing strategy based on the proposed systolic dataflow achieves less hardware overhead compared with other strategies, and the reuse of image values and weight values, which effectively reduce the power of memory access. A memory system with a multi-level storage structure combined with register file (RF) and SRAM is used in the proposed CNN processor, which further reduces the energy overhead of computing. The proposed CNN processor architecture has been verified on a ZC706 FPGA platform using VGG-16 based on the proposed image segmentation method, the evaluation results indicate that the peak throughput achieves 115.2 GOP/s consuming 3.801 W at 150 MHz, energy efficiency and DSP efficiency reaches 30.32 GOP/s/W and 0.26 GOP/s/DSP, respectively.

In this paper, an 8/16x time amplifier (TA) using ring oscillator (ROSC) is presented. For a wide input range, a time register (TR) based on gated ring oscillator (GRO) is proposed which has a variable capacity and can realize the accumulation and subtraction of time. Together with the proposed double multiplication phase detector (PD), the TA is implemented, which achieves a wide input range of more than ±200ps, and programmable gain without any calibration. The gain error is less than ±4.5% in all gain modes under various process, voltage, and temperature (PVT), while consuming 477uw with a 30MHz sampling frequency. The TA has no areaintensive passive devices and occupies an area of 0.0068mm ² in 130nm CMOS process. In addition, by adjusting the capacity of TR, a higher throughput rate or a wider input range can be selected for TA according to the actual requirement.