This article presents a 60-mode high-throughput parallel-processing memory-based fast Fourier transform (FFT) processor for fifth-generation (5G)/4G applications. The proposed architecture adopts a multi-FFT parallel-processing scheme to significantly reduce the idle computation cycles of small point FFT due to the deep pipeline. The proposed scheme can narrow the throughput gap between different FFT sizes. In conjunction with the parallel processing scheme, a configurable 16-parallelism butterfly unit is proposed to support a maximum of five radix-3, four radix-4, three radix-5, two radix-8, or one radix-9 operation in one cycle. Furthermore, this article demonstrates conflict-free memory access with a parallel method based on fusion shift combined with a hopping-based method to simplify the data arrangement at different radix stages. According to the orthogonal frequency division multiplexing (OFDM) application characteristics, our processor is extended to support many additional commonly used functions, such as zero padding, cyclic prefix insertion, and 7.5-kHz frequency shift, which can simplify the system call in 5G/4G applications. The FFT processor has been successfully integrated into a small-cell base station baseband system-on-chip (SoC) and taped out at the TSMC 12-nm technology. The implementation result reveals that the die area of the proposed processor is 0.374 mm2 with a power consumption of 235.5 mW at 1 GHz, and the processor supports a balanced throughput up to 3.92 GS/s at all 60-mode, which is better than that of the state-of-the-art (SOTA) designs.

This letter focuses on the secure downlink multi-user generalized spatial modulation (MU-GSM) system based on the artificial noise (AN). Block diagonalization (BD) is firstly used to eliminate inter-user interference. In addition, the AN which has no impact on legitimate users is adopted to prevent eavesdropping for the first time in MU-GSM communication. Particularly, the proposed MU-GSM system can achieve satisfying security performance even without AN, which is different from the single-user scenario. Finally, the simulation results show that with AN protection and BD, the physical layer security can be significantly enhanced when compared with the random noise scheme and the multi-user precoding-aided spatial modulation.

In this paper, the hybrid technique of eighth-mode substrate integrated waveguide (EMSIW), coplanar waveguide (CPW) resonator, and complementary split-ring resonator (CSRR) is studied. On this basis, two compact bandpass filters (BPFs) with a controllable band based on EMSIW are proposed in this paper. Filter I embeds a CPW resonator between two cascaded EMSIW resonators, increasing the coupling of the two cavities without increasing the circuit size. Filter II is loaded with CSRRs between each of the EMSIW cavities. The fundamental mode of the SIW cavity and CSRR mode generates two separate passbands that can be independently controlled. The coupling topology and working principle of the two filters are illustrated through eigenmode simulation, field distribution analysis, and equivalent circuit model analysis. Compared with the reported works, both filters have compact size (0.33 λg × 0.33 λg), and high slope selectivity in addition to a tunable passband.

Progressive low-density parity check (LDPC) code decoding has been widely used to correct increasing raw bit errors in NAND Flash memory. Once the decoding of a single logical page fails, the read-retry operation will reprocess at an increased read level with more accurate initial log-likelihood ratio (LLR) messages. However, the traditional progressive LDPC decodings with inappropriate read-level-increase granularities of read-retry operations introduce unnecessary flash read latency. By taking advantage of globally coupled LDPC (GC-LDPC) codes, an improved adaptive granularity progressive LDPC decoding (IAGPD) is proposed. This method can estimate the number of uncorrectable bit errors before each read-retry operation by detecting the unsatisfied local parity checks and general syndrome in the decoding failure. Then, it adaptively selects the optimal read-level-increase granularities for read-retry operations in the progressive LDPC decoding. Compared with the existing decoding methods, only by an extra 0.098% of the decoder area and two clock cycles, our method can reduce the flash read latency by up to 43%. And the solid-state drive (SSD) read response time on MQsim can be reduced by up to 32%.

Electronically tuned bandpass filters are crucial frequency-selective devices in tunable RF front-ends and are extensively utilized in the fields of communications and sensing. For low-cost and easy integration, varactor based tunable microstrip filters have been widely used in circuit design. The miniaturization, tuning flexibility, and performance optimization of tunable microstrip filters are all areas of concern. This paper reviews the research conducted on the varactor-diode-based tunable bandpass filters over the past decade. Numerous filters with various structures are introduced in the following sequence: frequency tuning, frequency and bandwidth tuning, transmission zero tuning, and tunable bandpass filter with special functions. The existing problems and limitations of various types of tuned filters have been discussed. The performance of several outstanding works has been analyzed and compared. Finally, the development direction of varactor-based microstrip tunable filters is objectively summarized, which will advance the research of microstrip filters.

Nowadays, with the increasing performance requirements of wireless applications, the RF front end needs enough dynamic range to work properly in multiband. The traditional multichannel parallel structure provides outstanding performance, but repeated components consume a large board area and add complexity to the circuit [1] . To solve this problem, tunable architectures have been proposed [2] , [3] . At the same time, wireless telecommunication equipment is pushing toward low-cost system-on-chip technology, which integrates the RF front-end module with the back end onto a single chip.