In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence^® Virtuoso and Cadence^® Virtuoso Assura tools. From the front-end design of the 8 × 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power–delay product when compared to existing multiplier architectures. A further reduction in the power–delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications.

The formation of shrinkage cracks is a natural phenomenon in expansive soils. The development of these cracks affects both the physical and mechanical properties of the soil. This paper proposes new procedures for predicting and detecting the formation of crack patterns in expansive soils, based on customized Convolution Neural Network (CNN) and transfer learning. A total of four different deep learning models are developed to detect the soil crack pattern by changing the convolution layers and hyper-parameters in the analysis. The novelty of the proposed detection methods lies in the use of customized CNN models in shrinkage crack detection for expansive soils. The customized CNN models are constructed by varying the number of convolution layers and the hyperparameters. The results show that the proposed CNN models provide very accurate results and are capable of detecting the presence of cracks in the soil with great accuracy. The best results are from one of the customized CNN models namely the Customized CNN Model 2 which consists of five convolution layers, three activation layers, one pooling layer, two fully connected layers, and a softmax layer. The results from this model are compared with other well-known approaches from the literature and are shown to provide improved results. Overall, the proposed deep learning methods developed in this paper produce excellent results in terms of the accurate detection of shrinkage soil cracks and can also be applied to other types of soil cracks.

Multiply–Accumulate (MAC) units are essential components in real-time Digital Signal Processing (DSP) applications such as image filtering, audio processing, and neural networks, where speed and energy efficiency are critical. This work presents a scalable and automated Hardware Description Language (HDL) generation framework for efficient MAC unit design, enabling faster integration into System-on-Chip (SoC) architectures. A Python automation script is developed to generate synthesizable Verilog code supporting user-defined bit-widths and computation cycles. The framework integrates a Grouping and Decomposition (GD) multiplier with a carry-skip adder, enhancing computational speed and minimizing energy consumption through parallelized data processing. The generated Verilog code is functionally verified using Cadence ^® Nclaunch, while synthesis and physical implementation are performed using Cadence ^® Genus and Innovus tools across multiple technology nodes. Experimental evaluation shows that the 8-bit GD-based MAC implemented in 180 nm technology achieves 14.96times lower power, 9.86times improvement in Power Delay Product (PDP) and Energy per Operation (EOP), and 6.52times improvement in Energy Delay Product (EDP) compared to existing designs. Likewise, the 16-bit MAC in 90 nm technology achieves a 70.08% reduction in delay and a 91.2% improvement in EDP. Overall, the proposed framework delivers a scalable, energy-efficient, and automation-driven solution for high-performance MAC design.