Emerging applications of compact high-voltage SiC modules pose strong challenges in the module package insulation design. Such SiC module insulations are subjected to both high-voltage dc and pulsewidth modulation (PWM) excitations between different terminals during different switching intervals. High dV/dt strongly interferes with partial discharge (PD) testing as it is hard to distinguish PD pulses and PWM excitation-induced interferences. This article covers both the testing and modeling of PD phenomena in the high-voltage power modules. A high dV/dt PD testing platform is proposed, which involves a super-high-frequency (SHF) (SHF >3 GHz) down-mixing PD detection receiver and a high-voltage scalable square wave generator. The proposed method captures SHF PD signatures and determines PD inception voltage (PDIV) for packaging insulation. Using this platform, this article provides a group of PDIV comparisons of packaging insulation under dc and PWM waveforms and discloses discrepancies in these PDIV results with respect to their excitations. Based on these PD testing results, the article further provides a model using the space-charge accumulation to explain the PD difference under dc and PWM waveforms. Both simulation and sample testing results are included in this article to support this hypothesis. With this new model, the article includes an updated insulation design procedure for the high-voltage power modules.

Conventional passive EMI filters are bulky and occupy up to 30% of converter volume and weight. Active EMI filters are a key technology that enables the volume reduction of passive components in the EMI filter. The effectiveness of traditional active EMI filter for volume reduction is limited by the additional overhead from the passive components for noise sensing and compensation to ensure stability. In this article, a novel active EMI filter is proposed and demonstrated for differential mode noise attenuation. The filter consists of a twin circuit made up of low voltage/current components that mimic the high-power passive filter components in the main circuit. Unlike the conventional active EMI filter, the proposed filter uses compensation networks which consists of low-voltage surface-mount components only. The modeling of the entire circuit is carried out, and verified with small-signal measurements. The filter is then tested in a converter and the experimental results are shown to be consistent with the model and the small-signal measurements.

In the acceleration of deep neural network training, the graphics processing unit (GPU) has become the mainstream platform. GPUs face substantial challenges on Graph Neural Networks (GNNs), such as workload imbalance and memory access irregularities, leading to underutilized hardware. Existing solutions such as PyG, DGL with cuSPARSE, and GNNAdvisor frameworks partially address these challenges. However, the memory traffic involved with Sparse-Dense Matrix Matrix Multiplication (SpMM) is still significant. We argue that drastic performance improvements can only be achieved by the vertical optimization of algorithm and system innovations, rather than treating the speedup optimization as an "after-thought" (i.e., (i) given a GNN algorithm, designing an accelerator, or (ii) given hardware, mainly optimizing the GNN algorithm). In this paper, we present MaxK-GNN, an advanced high-performance GPU training system integrating algorithm and system innovation. (i) We introduce the MaxK nonlinearity and provide a theoretical analysis of MaxK nonlinearity as a universal approximator, and present the Compressed Balanced Sparse Row (CBSR) format, designed to store the data and index of the feature matrix after nonlinearity; (ii) We design a coalescing enhanced forward computation with row-wise product-based Sparse Matrix-Matrix Multiplication (SpGEMM) Kernel using CBSR for input feature matrix fetching and strategic placement of a sparse output accumulation buffer in shared memory; (iii) We develop an optimized backward computation with outer product-based and Sampled Sparse Matrix Dense Matrix Multiplication (SSpMM) Kernel. We conduct extensive evaluations of MaxK-GNN and report the system training time. Experiments show that MaxK-GNN system could approach the speedup limit according to Amdahl's law. We achieve comparable accuracy to SOTA GNNs, but at a significantly increased speed: 3.22×/4.24× speedup (vs. 5.52×/7.27×) on Reddit compared to DGL and GNNAdvisor implementations. Our implementation can be found on GitHub¹.

SiC wide bandgap semiconductors offer significant improvement in high voltage and high-temperature stability; however, their associated packaging often can impede electrical performance and reliability. In this study, a new flip-chip package, implementing a vertically oriented MOSFET was investigated to achieve co-optimized thermomechanical reliability with low parasitic inductance. The architecture improves upon wire-bonded packages by allowing for top side cooling and reduced power loop inductance. Herein, the design effects of solder material and diameter as well as pitch size and drain connector geometry on thermal cycling reliability of the device were investigated using finite element methods. Additionally, thermal resistance in association with parasitic inductance of varying drain connector architectures is compared, while utilizing symmetry to facilitate manufacturability. By considering the complex effects of geometry and material, the optimal architecture was selected and fabricated. When comparing to a prior flip-chip design effort, this simulation-based design optimization was able to improve the solder fatigue life up to 11 times, while reducing parasitic inductance by 30 times. Experimentally, the associated electrical performance of the novel device showed improved switching behavior in double-pulse testing of a half-bridge module, with nearly-negligible overshoot voltage on switching; where an equivalent discrete package exhibited ~100% overshoot, and ~24% inductance improvement at the module level.