The 32-bit floating-point (FP32) binary format, commonly used for data representation in computers, introduces high complexity, requiring powerful and expensive hardware for data processing and high energy consumption, hence being unsuitable for implementation on sensor nodes, edge devices, and other devices with limited hardware resources. Therefore, it is often necessary to use binary formats of lower complexity than FP32. This paper proposes the usage of the 24-bit fixed-point format that will reduce the complexity in two ways, by decreasing the number of bits and by the fact that the fixed-point format has significantly less complexity than the floating-point format. The paper optimizes the 24-bit fixed-point format and examines its performance for data with the Laplacian distribution, exploiting the analogy between fixed-point binary representation and uniform quantization. Firstly, the optimization of the 24-bit uniform quantizer is performed by deriving two new closed-form formulas for a very accurate calculation of its maximal amplitude. Then, the 24-bit fixed-point format is optimized by optimization of its key parameter and by proposing two adaptation procedures, with the aim to obtain the same performance as of the optimal uniform quantizer in a wide range of variance of input data. It is shown that the proposed 24-bit fixed-point format achieves for 18.425 dB higher performance than the floating-point format with the same number of bits while being less complex.

Motivated by the fact that uniform quantization is not suitable for signals having non-uniform probability density functions (pdfs), as the Laplacian pdf is, in this paper we have divided the support region of the quantizer into two disjunctive regions and utilized the simplest uniform quantization with equal bit-rates within both regions. In particular, we assumed a narrow central granular region (CGR) covering the peak of the Laplacian pdf and a wider peripheral granular region (PGR) where the pdf is predominantly tailed. We performed optimization of the widths of CGR and PGR via distortion optimization per border–clipping threshold scaling ratio which resulted in an iterative formula enabling the parametrization of our piecewise uniform quantizer (PWUQ). For medium and high bit-rates, we demonstrated the convenience of our PWUQ over the uniform quantizer, paying special attention to the case where 99.99% of the signal amplitudes belong to the support region or clipping region. We believe that the resulting formulas for PWUQ design and performance assessment are greatly beneficial in neural networks where weights and activations are typically modelled by the Laplacian distribution, and where uniform quantization is commonly used to decrease memory footprint.

This paper introduces a novel approach that bridges the floating-point (FP) format, widely utilized in diverse fields for data representation, with the μ-law companding quantizer, proposing a method for designing and linearizing the μ-law companding quantizer to yield a piecewise uniform quantizer tailored to the FP format. A key outcome of the paper is a closed-form approximate expression for closely and efficiently evaluating the FP format’s performance for data with the Laplacian distribution. This expression offers generality across various bit rates and data variances, markedly reducing the computational complexity of FP performance evaluation compared to prior methods reliant on summation of a large number of terms. By facilitating the evaluation of FP format performance, this research substantially aids in the selection of the optimal bit rates, crucial for digital representation quality, dynamic range, computational overhead, and energy efficiency. The numerical calculations spanning a wide range of data variances provided for some commonly used FP versions with an 8-bit exponent have demonstrated that the proposed closed-form expression closely approximates FP format performance.

The 32-bit floating-point (FP32) format has many useful applications, particularly in computing and neural network systems. The classic 32-bit fixed-point (FXP32) format often introduces lower quality of representation (i.e., precision), making it unsuitable for real deployment, despite offering faster computations and reduced computational cost, which positively impacts energy efficiency. In this paper, we propose a switched FXP32 format able to compete with or surpass the widely used FP32 format across a wide variance range. It actually proposes switching between the possible values of key parameters according to the variance level of the data modeled with the Laplacian distribution. Precision analysis is achieved using the signal-to-quantization noise ratio (SQNR) as a performance metric, introduced based on the analogy between digital formats and quantization. Theoretical SQNR results provided in a wide range of variance confirm the design objectives. Experimental and simulation results obtained using neural network weights further support the approach. The strong agreement between the experiment, simulation, and theory indicates the efficiency of this proposal in encoding Laplacian data, as well as its potential applicability in neural networks.

The aim of this paper is to design, analyze and compare four different systems for ADC (analog-to-digital conversion) of vibration signals. Measurement of vibration signals is of particular importance in many areas, such as predictive maintenance or structural health monitoring. Wireless systems for vibration measurements becomes very topical, due to much easier and cheaper installation compared to wired systems. Due to the lack of transmission bandwidth and energy in wireless measurement systems, the amount of digital data being sent has to be reduced; hence, we have to apply ADC systems that can achieve the required digital signal quality, reducing the bit-rate. Four ADC systems are analyzed, for possible application in wireless measurement systems: PCM (pulse code modulation) based on uniform quantization; DPCM (differential PCM) to exploit high correlation of vibration signals; two adaptive ADC systems to cope with significant variations of characteristics of vibration signals in time - APCM (adaptive PCM) with adaptation on variance and ADPCM (adaptive DPCM), with double adaptation (both on variance and correlation). These ADC models are designed and optimized specifically for vibration signals, based on the analysis of 20 vibration signals from a referent database. An experiment is done, applying designed ADC systems for digitalization of vibration signals. APCM, DPCM and ADPCM systems allow significant bit-rate reduction compared to the PCM system, but with the increasing of complexity, hence the compromise between the bit-rate reduction and complexity is needed.

Pseudorandom absolute position encoders represent an advanced version of the widely used absolute position encoders, particularly suitable for high-resolution angular position measurement. This paper presents a detailed performance analysis of the pseudorandom absolute position encoder with embedded serial pseudorandom/natural code converter, focusing on the maximum operating frequency and the absolute error in angular position measurement. The generalized analysis, applicable to various resolution values, represents a significant contribution of the paper. Determining the maximum operating frequency involves a detailed analysis of propagation delays in the serial code converter circuit. It is demonstrated that encoder resolution profoundly impacts performance, with a dual effect: higher resolution decreases the absolute error but also reduces the maximum operating frequency, necessitating the determination of the most suitable resolution value for each specific application. In addition to its theoretical importance, the generalized analysis aids practical application by facilitating performance calculations and the selection of the most suitable resolution for specific applications. The performance evaluation was conducted for code converters implemented using the widely used 74LVC logic circuits, considering a 6-bit converter as a representative example of converters with a single XOR logic gate in the feedback loop of the shift register, and an 8-bit converter as a representative example of serial converters with three XOR logic gates in the feedback loop. By applying the proposed analysis, the maximum clock frequency was determined to be 29.85 MHz for both resolution values (6 and 8 bits). Simulations in NI Multisim software validate the performed analysis, showing a strong correlation between simulation and theoretical results.