Convolutional Neural Network (CNN) has attained high accuracy and it has been widely employed in image recognition tasks. In recent times, deep learning-based modern applications are evolving and it poses a challenge in research and development of hardware implementation. Therefore, hardware optimization for efficient accelerator design of CNN remains a challenging task. A key component of the accelerator design is a processing element (PE) that implements the convolution operation. To reduce the amount of hardware resources and power consumption, this article provides a new processing element design as an alternate solution for hardware implementation. Modified BOOTH encoding (MBE) multiplier and WALLACE tree-based adders are proposed to replace bulky MAC units and typical adder tree respectively. The proposed CNN accelerator design is tested on Zynq-706 FPGA board which achieves a throughput of 87.03 GOP/s for Tiny-YOLO-v2 architecture. The proposed design allows to reduce hardware costs by 24.5% achieving a power efficiency of 61.64 GOP/s/W that outperforms the previous designs.

Deep neural networks (DNN) have been a hot research topic in recent years. The key element of DNN is to explore the real time hardware implementation. However, it requires a complete knowledge of hardware where the DNN is going to be implemented. The computational complexity and resource consumption of DNN is increasing by the time. Convolutional Neural Network (CNN) is the popular architecture of DNN especially for image classification. One requires an efficient implementation strategy of CNN to incorporate more computations in real time. Field Programmable Gate Array (FPGA) is considered to be the energy efficient choice for CNN as compared to Graphical Processing Units (GPUs). In this paper, new idea is explored and implemented for basic Processing Element (PE) of CNN. FPGA has limited built-in multiplier accumulator (MAC) units. In this work, MAC units are replaced by Wallace Tree based Multiplier which belongs to the family of log time array multipliers. The resources are saved in terms of MAC units and we can implement more processing elements on FPGA.

As the average age of the population goes higher, the people undergo hip arthroplasty surgery to replace their stiff and painful damaged hip joints. To reduce the risk factor after the surgery we developed a visual aided system in previous works. In order to solve the integration problems of commercial camera with other sensors into the femoral head and to minimize the area and power consumption, in this paper we propose a CMOS image sensor of resolution 200 × 200 specially designed for the application in which each individual pixel measures around 15 μm × 15 μm in size and the image sensor chip size measures about 3.5 mm × 3.5 mm. The proposed sensor is simulated with the input current variations from 2 pA to 100 pA for the individual pixels and the corresponding measurements for each pixel range from 2 mV to 855 mV. Besides, we put forward a new method of pattern detection and recognition in the blood-covered situation, which provides an accurate segmentation of patterns from the blood. All the detected patterns are recognized by generating its right 9-bit binary ID required for the pose estimation calculation. Furthermore, to reduce system power consumption, we implement algorithms on FPGA to process the image data pixel by pixel and transmit it directly to the computer for post-processing. Experimental results show that the pattern detection rate goes as high as 99%, which is 5% better in accuracy compared to the top hat algorithm. The power consumption of the system is 213 mW, which is a 70% decrease compared to our previous work.

The selection of the optimizer is critical for convergence in the field of on-chip training. As one second moment optimizer, adaptive moment estimation (ADAM) shows a significant advantage compared with non-moment optimizers such as stochastic gradient descent (SGD) and first-moment optimizers such as Momentum. However, ADAM is hard to implement on hardware due to the computationally intensive operations, including square, root extraction, and division. This work proposed Hardware-ADAM (HW-ADAM), an efficient fixed-point accelerator for ADAM highlighting hardware-oriented mathematical optimizations. HW-ADAM has two designs: Efficient-ADAM (E-ADAM) unit reduced the hardware resource consumption by around 90% compared with the related work. E-ADAM achieved a throughput of 2.89 MUOP/s (Million Updating Operation per Second), which is 2.8× of the original ADAM. Fast-ADAM (F-ADAM) unit reduced 91.5% flip-flops, 65.7% look-up tables, and 50% DSPs compared with the related work. The F-ADAM unit achieved a throughput of 16.7 MUOP/s, which is 16.4× of the original ADAM.

In conventional DFT based orthogonal frequency division multiplexing (OFDM), cyclic prefix (CP) is used to avoid the inter symbol interference (ISI) caused by a time dispersive channel. A solution has been proposed in literature, which involves replacing DFT with wavelet packet transform (WPT) in communication systems. WPT does not require CP and has the attraction of having much lower side lobes. However, in wavelet based multicarrier systems, channel equalization remains an open research area. In this article, a time-domain zero-forcing equalizer (ZFE) for wavelet packet based OFDM (WOFDM) is proposed. The performance comparison of DFT-OFDM and WOFDM is given for an arbitrary FIR channel with different types of wavelet packets. Simulation results show improvement in bit error rate (BER) performance for WOFDM.

Convolutional Neural Network (CNN) is a very popular method in recent times to solve many computer vision tasks. However, CNN is becoming computationally intensive as time is progressing which requires a dedicated hardware for real time implementation. Graphics Processing Unit (GPU) and Field Programmable Gate Array (FPGA) are two hot choices to execute and accelerate the CNN network. FPGA has an advantage over GPU due to its flexible architecture and it can also provide high performance per unit watt of power. These benefits make FPGA a suitable candidate for CNN acceleration. However, optimization is required for FPGA based accelerator design to accommodate more computations. One of the challenges in accelerator design is to perform addition of intermediate results generated in a process of convolution. Therefore, Multi-Operand Adders (MOAs) are necessary in the accelerator design of CNN on FPGA but consume most of the area. Optimization strategy based on WALLACE tree architecture is proposed in this article to replace the typical binary adder tree in CNN accelerator design. Experimental results show an improvement in terms of area optimization and performance in comparison with the previous implementation.