Convolutional Neural Network (CNN) has attained high accuracy and it has been widely employed in image recognition tasks. In recent times, deep learning-based modern applications are evolving and it poses a challenge in research and development of hardware implementation. Therefore, hardware optimization for efficient accelerator design of CNN remains a challenging task. A key component of the accelerator design is a processing element (PE) that implements the convolution operation. To reduce the amount of hardware resources and power consumption, this article provides a new processing element design as an alternate solution for hardware implementation. Modified BOOTH encoding (MBE) multiplier and WALLACE tree-based adders are proposed to replace bulky MAC units and typical adder tree respectively. The proposed CNN accelerator design is tested on Zynq-706 FPGA board which achieves a throughput of 87.03 GOP/s for Tiny-YOLO-v2 architecture. The proposed design allows to reduce hardware costs by 24.5% achieving a power efficiency of 61.64 GOP/s/W that outperforms the previous designs.

An ultra-low power ECG processor ASIC (application specific integrated circuit) with R-wave detection and data compression is presented, which is designed for the long-term implantable cardiac monitoring (ICM) device for arrhythmia diagnosis. An adaptive derivative-based detection algorithm with low computation overhead for potential arrhythmia recording is proposed to detect arrhythmia with the occasional abnormal heart beats. In order to save as much as possible cardiac information with the limited memory size available in the ICM device, a hierarchical data buffer structure is proposed which saves 3 types of data, including the raw ECG data segments of 2 seconds, compressed ECG data segments of 45 seconds, and R-peak values and interval lengths of >2000 beat cycles. A modified swinging-door-trending (SDT) method is proposed for the ECG data compression. The ASIC has been implemented based on fully-customized near-threshold standard cells using the thick-gate transistors in 65-nm CMOS technology for low dynamic power consumption and leakage. The ASIC core occupies a die area of 1.77 mm ² . The measured total power is 2.63 μW, which is among the ECG processors with the lowest core power consumption. It exhibits a relatively high positive precision rate ( P ₊ ) of 99.3% with a sensitivity of 98.2%, in contrast to the similar designs in literature with the same core power consumption level. Also, an ECG data compression ratio ( CR ) of up to 17.0 has been achieved, with a good trade-off between the compression efficiency and loss.

Bowel sounds (BSs), typically generated by the intestinal peristalses, are a significant physiological indicator of the digestive system's health condition. In this study, a wearable BS monitoring system is presented for long-term BS monitoring. The system features a wearable BS sensor that can record BSs for days long and transmit them wirelessly in real-time. With the system, a total of 20 subjects' BS data under the hospital environment were collected. Afterward, CNNs are introduced for BS segment recognition. Specifically, this study proposes a novel CNN design method that makes it possible to transfer the popular CNN modules in image recognition into the BS segmentation domain. Experimental results show that in holdout evaluation with corrected labels, the designed CNN model achieves a moderate accuracy of 91.8% and the highest sensitivity of 97.0% compared with the similar works. In cross validation with noisy labels, the designed CNN delivers the best generability.

This paper proposes a low power and efficient QRS processor for real-time and continuous mobile ECG monitoring. The QRS detector contains the wavelet transform (WT), the modulus maxima pair identification (MMPI), and the R position modification (RPM). In order to reduce power consumption, we choose the Haar function as the mother wavelet of WT. It is implemented by an optimized FIR filter structure where none of the multiplier is used. The MMPI processes the wavelet coefficients at scale 2 ⁴ and provides candidate R peak positions for the RPM. To improve the accuracy and robust performance, a number of modules have been designed in MMPI, including the preprocessing unit, the automatic threshold updating, and the decision state machine. The RPM is designed to eliminate digital time delay in wavelet transform and locate the R peak position precisely. Raw ECG signals and QRS detection results are output simultaneously. Fabricated in 0.18-μm N-well CMOS 1P6M technology, the power consumption of this chip is only about 410 nW in 1 V voltage supply. Validated by all 48 sets of data in the MIT-BIH arrhythmia database, the sensitive and the positive prediction are 99.60% and 99.77% respectively.

A wireless intracranial pressure (ICP) monitoring system based on the air pressure sensing is proposed in this work. The proposed system is composed of an implantable ICP sensing device and a portable wireless data recorder. The ICP sensing device consists of an air pressure sensor, an ultra-thin air pouch for pressure sensing, and a low-power dedicated system-on-a-chip (SoC) for the data acquisition control and wireless transmission. The SoC consists of a power management unit, a wake-up controller, the sensor interface, a wireless transmitter, and the workflow control logic. The SoC is fabricated in 0.18 μm CMOS technology with a die area of 3.04 mm × 2 mm. Experimental results show that the prototype implantable ICP device has achieved a resolution of 0.2 mmHg and a battery lifetime of 1 week with a 3 V 50 mAh battery. The ICP device has been tested in the liquid environment. The nonlinearity error is less than ±0.4 mmHg for the full measurement range of -20 to +150 mmHg. Compared to the other implantable wireless ICP solutions in the literature, the proposed system alleviates the biocompatibility issue and increases the measurement accuracy.