In this paper, we propose a method for reconstructing synthetic aperture radar (SAR) images by applying a compressive sensing (CS) technique to sparsely acquired radar sensor data. In general, SAR image reconstruction algorithms require radar sensor data acquired at regular spatial intervals. However, when the speed of the radar-equipped platform is not constant, it is difficult to consistently perform regular data acquisitions. Therefore, we used the CS-based signal recovery method to efficiently reconstruct SAR images even when regular data acquisition was not performed. In the proposed method, we used the l1-norm minimization to overcome the non-uniform data acquisition problem, which replaced the Fourier transform and inverse Fourier transform in the conventional SAR image reconstruction method. In addition, to reduce the phase distortion of the recovered signal, the proposed method was applied to each of the in-phase and quadrature components of the acquired radar sensor data. To evaluate the performance of the proposed method, we conducted experiments using an automotive frequency-modulated continuous wave radar sensor. Then, the quality of the SAR image reconstructed with data acquired at regular intervals was compared with the quality of images reconstructed with data acquired at non-uniform intervals. Using the proposed method, even if only 70% of the regularly acquired radar sensor data was used, a SAR image having a correlation of 0.83 could be reconstructed.

In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

Synthetic aperture radar (SAR), which can generate images of regions or objects, is an important research area of radar. The chirp scaling algorithm (CSA) is a representative SAR imaging algorithm. The CSA has a simple structure comprising phase compensation and fast Fourier transform (FFT) operations by replacing interpolation for range cell migration correction (RCMC) with phase compensation. However, real-time processing still requires many computations and a long execution time. Therefore, it is necessary to develop a hardware accelerator to improve the speed of algorithm processing. In addition, the demand for a small SAR system that can be mounted on a small aircraft or drone and that satisfies the constraints of area and power consumption is increasing. In this study, we proposed a CSA-based SAR processor that supports FFT and phase compensation operations and presents field-programmable gate array (FPGA)-based implementation results. We also proposed a modified CSA flow that simplifies the traditional CSA flow by changing the order in which the transpose operation occurs. Therefore, the proposed CSA-based SAR processor was designed to be suitable for modified CSA flow. We designed the multiplier for FFT to be shared for phase compensation, thereby achieving area efficiency and simplifying the data flow. The proposed CSA-based SAR processor was implemented on a Xilinx UltraScale+ MPSoC FPGA device and designed using Verilog-HDL. After comparing the execution times of the proposed SAR processor and the ARM cortex-A53 microprocessor, we observed a 136.2-fold increase in speed for the 4096 × 4096-pixel image.

Intelligent video surveillance systems detect pre-configured surveillance events through background modeling, foreground and object extraction, object tracking, and event detection. Shadow regions inside video frames sometimes appear as foreground objects, interfere with ensuing processes, and finally degrade the event detection performance of the systems. Conventional studies have mostly used intensity, color, texture, and geometric information to perform shadow detection in daytime video, but these methods lack the capability of removing shadows in nighttime video. In this paper, a novel shadow detection algorithm for nighttime video is proposed; this algorithm partitions each foreground object based on the object’s vertical histogram and screens out shadow objects by validating their orientations heading toward regions of light sources. From the experimental results, it can be seen that the proposed algorithm shows more than 93.8% shadow removal and 89.9% object extraction rates for nighttime video sequences, and the algorithm outperforms conventional shadow removal algorithms designed for daytime videos.

This paper explores novel architectures for fast backprojection based video synthetic aperture radar (BP-VISAR) with multiple GPUs. The video SAR frame rate is analyzed for non-overlapped and overlapped aperture modes. For the parallelization of the backprojection process, a processing data unit is defined as the phase history data or range profile data from partial synthetic-apertures divided from the full resolution target data. Considering whether full-aperture processing is performed and range compression or backprojection are parallelized on a GPU basis, we propose six distinct architectures, each having a single-stream pipeline with a single GPU. The performance of these architectures is evaluated in both non-overlapped and overlapped modes. The efficiency of the BP-VISAR architecture with sub-aperture processing in the overlapped mode is accelerated further by filling the processing gap from the idling GPU resources with multi-stream based backprojection on multiple GPUs. The frame rate of the proposed BP-VISAR architecture with sub-aperture processing is scalable with the number of GPU devices for large pixel resolution. It can generate 4096 × 4096 video SAR frames of 0.5 m cross-range resolution in 23.0 Hz on a single GPU and 73.5 Hz on quad GPUs.

In this paper, an adaptive block compressive sensing (BCS) method is proposed for compression of synthetic aperture radar (SAR) images. The proposed method enhances the compression efficiency by dividing the magnitude of the entire SAR image into multiple blocks and subsampling individual blocks with different compression ratios depending on the sparsity of coefficients in the discrete wavelet transform domain. Especially, a new algorithm is devised that selects the best block measurement matrix from a predetermined codebook to reduce the side information about measurement matrices transferred from the remote sensing node to the ground station. Through some modification of the iterative thresholding algorithm, a new clustered BCS recovery method is proposed that classifies the blocks into multiple clusters according to the compression ratio and iteratively reconstructs the SAR image from the received compressed data. Since the blocks in the same cluster are concurrently reconstructed using the same measurement matrix, the proposed structure mitigates the increase in computational complexity when adopting multiple measurement matrices. Using existing SAR images and experimental data obtained by self-made drone SAR and vehicular SAR systems, it is shown that the proposed scheme provides a good tradeoff between the peak signal-to-noise ratio and the computational load compared to conventional BCS-based compression techniques.