In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

Synthetic aperture radar (SAR), which can generate images of regions or objects, is an important research area of radar. The chirp scaling algorithm (CSA) is a representative SAR imaging algorithm. The CSA has a simple structure comprising phase compensation and fast Fourier transform (FFT) operations by replacing interpolation for range cell migration correction (RCMC) with phase compensation. However, real-time processing still requires many computations and a long execution time. Therefore, it is necessary to develop a hardware accelerator to improve the speed of algorithm processing. In addition, the demand for a small SAR system that can be mounted on a small aircraft or drone and that satisfies the constraints of area and power consumption is increasing. In this study, we proposed a CSA-based SAR processor that supports FFT and phase compensation operations and presents field-programmable gate array (FPGA)-based implementation results. We also proposed a modified CSA flow that simplifies the traditional CSA flow by changing the order in which the transpose operation occurs. Therefore, the proposed CSA-based SAR processor was designed to be suitable for modified CSA flow. We designed the multiplier for FFT to be shared for phase compensation, thereby achieving area efficiency and simplifying the data flow. The proposed CSA-based SAR processor was implemented on a Xilinx UltraScale+ MPSoC FPGA device and designed using Verilog-HDL. After comparing the execution times of the proposed SAR processor and the ARM cortex-A53 microprocessor, we observed a 136.2-fold increase in speed for the 4096 × 4096-pixel image.

This paper presents a polar-format algorithm (PFA)-based synthetic-aperture radar (SAR) processor that can be mounted on a small drone to support video SAR (ViSAR) imaging. For drone mounting, it requires miniaturization, low power consumption, and high-speed performance. Therefore, to meet these requirements, the processor design was based on a field-programmable gate array (FPGA), and the implementation results are presented. The proposed PFA-based SAR processor consists of both an interpolation unit and a fast Fourier transform (FFT) unit. The interpolation unit uses linear interpolation for high speed while occupying a small space. In addition, the memory transfer is minimized through optimized operations using SAR system parameters. The FFT unit uses a base-4 systolic array architecture, chosen from among various fast parallel structures, to maximize the processing speed. Each unit is designed as a reusable block (IP core) to support reconfigurability and is interconnected using the advanced extensible interface (AXI) bus. The proposed PFA-based SAR processor was designed using Verilog-HDL and implemented on a Xilinx UltraScale+ MPSoC FPGA platform. It generates an image 2048 × 2048 pixels in size within 0.766 s, which is 44.862 times faster than that achieved by the ARM Cortex-A53 microprocessor. The speed-to-area ratio normalized by the number of resources shows that it achieves a higher speed at lower power consumption than previous studies.

This paper presents a quantitative design space exploration of fast Fourier transform (FFT) architectures and numerical formats for frequency-modulated continuous-wave (FMCW) radar processing on system-on-chip (SoC) platforms. Three hardware architectures were implemented and evaluated: a memory-based single-butterfly (SB) architecture, a pipelined single-path delay-feedback (SDF) architecture, and a parallel systolic-array (SA) architecture. Two numerical formats–32-bit fixed-point (FX32) and 16-bit half-precision floating-point (FP16)–were compared in terms of latency, throughput, accuracy, and hardware efficiency. Experimental results show that the SB architecture achieves the highest resource efficiency, processing 43.72 MFrame/s per LUT and 13.68 KFrame/s per DSP in FX32, and 37.60 MFrame/s per LUT and 35.10 KFrame/s per DSP in FP16. While FP16 slightly increases LUT utilization, it significantly enhances efficiency in DSP, FF, and BRAM resources, leading to more balanced hardware utilization overall. The SA architecture delivers the shortest latency and reducing range–Doppler-map (RDM) generation time by approximately 15.61% compared with SB, albeit at the cost of over 8.9× LUT and 6.5× DSP consumption. The SDF architecture achieves moderate throughput suitable for streaming but is constrained by memory bandwidth in SoC environments. From an architectural perspective, the SB design provides the best hardware efficiency, whereas from a numerical-format perspective, FP16 offers the most favorable trade-off between precision and resource usage. At the system level, increasing the AXI data width improved processing speed by 20–26%, while burst length tuning provided smaller gains of 4–5%. The results presented in this work provide practical design guidelines for implementing efficient FFT accelerators in SoC-based FMCW radar systems.

This paper presents a field-programmable gate array (FPGA)-based hardware accelerator for the frequency scaling algorithm (FSA) targeting real-time onboard synthetic aperture radar (SAR) imaging. System performance is typically bottlenecked by repeated dynamic random-access memory (DRAM) accesses during fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operations, bit-reversal data reordering, complex phase multiplications, and matrix transpositions. The proposed architecture integrates three hardware optimizations. First, a Parallel Feedback FFT block combines decimation-in-time (DIT) and decimation-in-frequency (DIF) FFT structures with complementary input/output ordering. This block executes the range-domain processing stages continuously in an on-chip feedback pipeline, eliminating intermediate DRAM transactions and reordering buffers while processing two range lines simultaneously. Second, a coordinate rotation digital computer (CORDIC)-based on-chip Phase Generation and Multiplication block generates phase factors directly within the programmable logic (PL). By precombining phase terms and employing mixed-precision—double-precision (FP64) and half-precision (FP16) floating-point—it reduces hardware resource consumption while maintaining high numerical accuracy. Third, a Partitioned Transpose block enables large-scale matrix transpositions within limited block RAM (BRAM), mitigating column-wise bottlenecks while preserving efficient external DRAM burst access. Implemented on a Xilinx Zynq UltraScale+ multiprocessor system-on-chip (MPSoC) ZCU104, it processes a 16384×16384 SAR image in 14.456 s. This achieves a 465× speedup over an ARM Cortex-A53 software baseline, and an 861× speedup in the range-domain processing stage. These results validate the architecture as a highly efficient, practical solution for real-time onboard SAR applications.