Condition monitoring (CM) is crucial for ensuring equipment reliability. Yet, its practical implementation encounters several challenges. On the one hand, these include hurdles in big data collection/storage, sensor selection/calibration/installation. On the other hand, developing effective CM techniques, especially for anomaly detection throughout the degradation process, requires extracting and selecting appropriate health indicators (HIs) and ensuring accurate anomaly detection. While bearings and gears have been intensively studied in the past, only little attention has been given to roller chain (RC) systems. Therefore, this study introduces an innovative approach leveraging a sensorless strategy and deep weighted K-nearest neighborhood (DWKNN) for detecting the abnormal status in RC systems. First, by utilizing readily available motor driver data, the need for expensive sensor selection/installation and data management is eliminated, enhancing cost-effectiveness and applicability across diverse industrial applications. Second, leveraging position information from the motor, the raw data are segmented, transformed into the frequency domain, and fused to provide a comprehensive understanding of the system’s behavior, thus improving CM performance. Subsequently, DWKNN entails intelligent indicator extraction and anomaly detection. Intelligent indicator extraction utilizes the deep sparse autoencoder (DSAE) method to dig hidden information in the acquired data and represent the degradation process. Meanwhile, anomaly detection is achieved through a weighted K-nearest neighborhood (WKNN), ensuring effectiveness and robustness. Through validation on multiple chains, the developed methodology demonstrates its effectiveness in addressing real-world CM challenges in industrial environments, offering a cost-effective and reliable solution compared with other methods.

Analog integrated circuit sizing is notoriously difficult to automate due to its complexity and scale; thus, it continues to heavily rely on human expert knowledge. This work presents a machine learning-based design automation methodology comprising pre-defined building blocks such as current mirrors or differential pairs and pre-computed look-up tables for electrical characteristics of primitive devices. Modeling the behavior of primitive devices around the operating point with neural networks combines the speed of equation-based methods with the accuracy of simulation-based approaches and, thereby, brings quality of life improvements for analog circuit designers using the $g_{\mathrm{m}}/I_{\mathrm{d}}$ method. Extending this procedural automation method for human design experts, we present a fully autonomous sizing approach. Related work shows that the convergence properties of conventional optimization approaches improve significantly when acting in the electrical domain instead of the geometrical domain. We, therefore, formulate the circuit sizing task as a sequential decision-making problem in the alternative electrical design space. Our automation approach is based entirely on reinforcement learning, whereby abstract agents learn efficient design space navigation through interaction and without expert guidance. These agents’ learning behavior and performance are evaluated on circuits of varying complexity and different technologies, showing both the feasibility and portability of the work presented here.

Research in design automation for power electronics (DAPE) is a growing subject propelled by the demand for power electronics in the light of electrification. This paper explains and transfers concepts found in microelectronics EDA to DAPE. A broad literature analysis via automated rule-based classification of more than 6 000 publications shows the dominant automation approaches in connection with popular tasks to automate, the focused components and respective applications. Besides this content analysis, an analysis over time provides insight into past and current trends. The paper concludes with a comparison to EDA found in analog IC design to outline possible future research directions in DAPE.

To this day, the design of analog integrated circuits is a predominantly manual task, heavily reliant on the knowledge and intuition of human experts. Many current automation approaches aim to be holistic solutions, attempting to take the human out of the loop. This work, in turn, does not intend to replace human designers with algorithms, but support their qualities in the established flow. Here, the performance space of analog ICs is modeled by PVT-aware neural networks and visualized with parallel coordinate plots. Such a responsive visualization gives insights into the relations of parameters through interactive exploration where any parameter can be the cause while all others show the immediate effect. Thus, complex decision-making problems based on the experience of seasoned designers, such as circuit sizing or topology selection, are transformed into intuitive perceptual problems. Through the responsiveness and immediacy of the implementation, designers are encouraged to explore the entire performance space instead of basing all decisions on previous designs, never leaving the beaten path. A data generation and training procedure for surrogate models is outlined. Models for three operational amplifiers in three different technologies illustrate the applicability and feasibility of the presented approach. Additionally, a web-based demo, including all source code, is available for review.