For 48 V mild hybrid vehicles, a sub-0.5 W, 48 V-to-5 V dc–dc converter fulfilling: 1) high efficiency with small volume; 2) constant switching frequency of less than 500 kHz to avoid the frequency band of AM radio; and 3) constant output voltage ( V _OUT ) against the sudden drop of input battery voltage ( V _IN ) under cold cranking is required. To meet the requirements, a 0.55 W, 88%, 78 kHz, 48 V-to-5 V Fibonacci hybrid (FH) dc–dc converter IC using 66 mm ³ of passive components is proposed. In the FH dc–dc converter, by adding an inductor and an output capacitor to a 1/5 Fibonacci switched-capacitor (SC) dc–dc converter, the SC dc–dc converter also works as a buck converter without adding power transistors. When V _IN drops from 48 V to 20 V in 1 ms in the automotive cold cranking, the FH dc–dc converter cannot keep 5-V V _OUT , because the output voltage of the internal 1/5 SC dc–dc converter drops from 9.6 to 4 V and the internal buck converter cannot generate 5-V V _OUT from 4 V. To solve the problem, a new control method named automatic change of converter topology and duty ratio (ACCD) is proposed. In ACCD, when V _IN drops less than 31 V, the converter topology automatically changes from 1/5 SC dc–dc converter to 1/3 SC dc–dc converter and the duty ratio of the pulsewidth modulation signal automatically decreases 3/5 times, thereby achieving the constant 5-V V _OUT under cold cranking. To reduce the volume of the FH dc–dc converter, all transistors and diodes, including ten power transistors, gate drivers, bootstrap circuits, and the controller, are fully integrated on 4.6 mm × 2.3 mm IC fabricated with 180 nm BCD process. In the measurements, the proposed 0.55 W, 48 V-to-5 V FH dc–dc converter IC achieved the highest efficiency (88%) with the smallest volume of passive components (66 mm ³ ) at the lowest switching frequency (78 kHz) compared with previous publications.

Digital active gate driving has been shown to effectively manage the switching performance for power devices with the adjustable driving waveforms. However, most of the studies are based on a dedicated test circuit rather than a practical inverter with the sinusoidal output current. In fact, it is the dependence on the load current that makes the design of the gate driving profiles a critical issue. To investigate the digital active gate driver in an inverter application, this article has applied optimal patterns adapting to time-varying output load current. Prior to the search of optimal patterns, the proper design of time slot is discussed with three different time resolutions. With the proper resolution determined for patterns, multiple optimizations are carried out for different current conditions. In this way, the search for optimal patterns can be completed in an efficient time. Next, a lookup table of optimal switching pattern in correspondence with each certain load current condition was built in advance. According to the output load current, the optimal pattern is selected based on the lookup table. Compared to conventional constant driving waveform, the power loss has been reduced by 7% with full optimal lookup table applied.

This article proposes a new optimization method and its platform for automatically adjusting the control parameters of a digital active gate driver while operating a pulse-width modulation (PWM) inverter. The proposed optimization method applies the searching parameters for some sectors in an ac current cycle and fixed parameters for the other sectors. This enables us to find the optimal operating points of power devices so as to reduce the surge voltage and switching loss with the consideration of their dependency on the load current. Additionally, the proposed optimization method also can find the operating points while the inverter performs a continuous switching operation. For this reason, the proposed optimization method can be applied to a continuous running test of PWM inverters, for example, in a manufacturing process. The validity of the proposed method and platform was evaluated by using a 10-kW three-phase PWM inverter with digital gate drives. The experimental results confirmed that the proposed optimization method makes it possible to find the optimal operating points for reducing the surge voltage and/or the power loss.

A 2/3 and 1/2 reconfigurable switched capacitor (SC) DC-DC converter is developed for a per-core dynamic voltage scaling of many-core microprocessors. The power conversion efficiency and the output power density of the SC DC-DC converter in 2/3 mode is degraded, because full-swing and half-swing drivers for power transistors are mixed and the resistive loss of the power MOSFETs with the half-swing drivers is large. To solve the problem, a fully-integrated driver amplitude doubler (DAD) is proposed. In DAD, the gate amplitude of the power MOSFETs is increased from half-swing to full-swing by generating a 1/3 input voltage sampled from a flying capacitor. In the fabricated 2.7-V input SC DC-DC converter mounting four 100-nF 0402 (0.4mm x 0.2mm x 0.2mm) multilayer ceramic chip capacitors (MLCCs) on 180-nm CMOS die achieves the highest efficiency of 92.9% at the output power density of 62mW/mm² in the published step-down SC DC-DC converters.

The step-up DC–DC converter is widely used for applications such as IoT sensor nodes, energy harvesting, and photovoltaic (PV) systems. In this article, a new topological quasi-Z-source (QZ) high step-up DC–DC converter for the PV system is proposed. The topology of this converter is based on the voltage-doubler circuits. Compared with a conventional quasi-Z-source DC–DC converter, the proposed converter features low voltage ripple at the output, the use of a common ground switch, and low stress on circuit components. The new topology, named a low-side-drive quasi-Z-source boost converter (LQZC), consists of a flying capacitor (C_F), the QZ network, two diodes, and a N-channel MOS switch. A 60 W laboratory prototype DC–DC converter achieved 94.9% power efficiency.

A Cascaded hybrid Fibonacci DC-DC converter with interleaved clock for DC grid is proposed. A hybrid Fibonacci stage is connected in series and the interleaved clock is applied. The modified converter is proposed by using two inductors in place of two switches of a typical X3 Fibonacci converter. By this modification, the converter achieved up to 20 of conversion rate (CR) at duty ratio of D = 0.84. The converter consists of two switches, three diodes, and three capacitors for a total of 10 elements. This component count is less than that of the past leading works of the high step-up DC-DC converters. The operation principle was verified using PSIM simulator. A laboratory prototype DC-DC converter achieved CR of 19.5 at D = 0.85.