Electrocardiography (ECG) is the most common and extensively used vital sign monitoring method in modern healthcare systems. Different designs of ambulatory ECG systems were developed as alternatives to the commonly used 12-lead clinical ECG systems. These designs primarily focus on portability and user convenience, while maintaining signal integrity and lowering power consumption. Here, a wireless ECG monitoring system is developed using flexible and dry capacitive electrodes for long-term monitoring of cardiovascular health. Our capacitive-coupled dry electrodes can measure ECG signals over a textile-based interface material between the skin and electrodes. The electrodes are connected to a data acquisition system that receives the raw ECG signals from the electrodes and transmits the data using Bluetooth to a computer. A software application was developed to process, store, and display the ECG signal in real time. ECG measurements were obtained over different types of textile materials and in the presence of body movements. Our experimental results show that the performance of our ECG system is comparable to other reported ECG monitoring systems. In addition, to put this research into perspective, recent ambulatory ECG monitoring systems, ECG systems-on-chip, commercial ECG monitoring systems, and different state-of-the-art ECG systems are reviewed, compared, and critically discussed.

In this paper, we propose an analytical model using the suppression factor for fast evaluation of the high-frequency channel noise in nanoscale MOSFETs for radio frequency and mixed-signal applications. The derived suppression factor expression can accurately predict the channel noise for both long- and short-channel MOSFETs working in all regions of operations. It only depends on two major process parameters, and enables early delivery of the noise models before conducting complicated high-frequency noise measurements. The model is verified using the experimental data measured on both n- and p-type MOSFETs fabricated in the 40-nm CMOS technology from United Microelectronics Corporation.

A shielded planar array of active slot antennas is proposed for applications in the microwave imaging of the breast. The frequency band is from 3 GHz to 8 GHz, where reflection loss better than 10 dB and inter-element mutual coupling less than –20 dB are achieved. The center-to-center element spacing is 12× 12 mm. A low-noise amplifier (LNA) is integrated with each antenna element for use in a receiving configuration. A ground plane within the multi-layer design separates the antenna array from the electronics array while providing shielding from the back and improving the power coupling into the tissue. The proposed structure resolves an outstanding problem in the design of large shielded antenna arrays for tissue imaging, namely, the interconnects between the array elements and the electronic circuits, which are separated by multiple dielectric layers and a grounded plane. The critical development is the new low-reflection triple-wire vertical transition that carries the signal from the antenna layer to the electronics layer while traversing through multiple layers of different permittivities and through openings in the ground plane. The design is verified by simulations and measurements. The passive and active designs are compared, illustrating the full utilization of the LNA gain. The performance of the proposed active array is also examined in imaging experiments with a compressed-breast phantom.

A simple, low-power and wearable health analyzer for early identification and management of some diseases is presented. To achieve this goal, we propose a walking pattern analysis system that uses features, such as speed, energy, turn ratio, and bipedal behavior to characterize and classify individuals in distinct walking-ages. A database is constructed from 74 healthy young adults in the age range from 18 to 60 years using the combination of inertial signals from an accelerometer and a gyroscope on a level path including turns. An efficient advanced signal decomposition method called improved complete ensemble empirical mode decomposition with adaptive noise (improved CEEMDAN) was used for feature extraction. Analyzes show that the gait of healthy able-bodied individuals exhibits a natural bipedal asymmetry to a certain level depending on the activity-type and age, which relate to individual's functional attributes rather than pathological gait. The analysis of turn ratio, a measure of activity-transition energy change and stability, indicated turning to be less locally stable than straight-line walking making it a more reliable measure for determining falls and other health issues. Extracted features were used to analyze two distinct walking-age groups of the healthy young adults based on their walking pattern, classifying 18-45 years old individuals in one group and 46-60 years old in the other group. Our proposed simple, inexpensive walking analyzer system can be easily used as an ambulatory screening tool by clinicians to identify at risk population at the early onset of some diseases.

The design of cryogenic CMOS electronics for quantum computing applications, including critical radio frequency blocks such as low noise amplifiers (LNAs), is hindered by the lack of mature RF and noise models for cryo-MOSFETs. In this paper, we study the temperature scaling trends of important MOSFET RF parameters and evaluate the noise performance of commonly-used LNAs at cryogenic temperatures. We show that traditional thermal-noise-based models significantly underestimate the noise of cryo-CMOS LNAs. Instead, we employ a shot-noise-based model that is relatively temperature independent to predict noise factors of cryo-CMOS LNAs, which are consistent with published experimental results. We provide analyses and guidelines to further improve their noise performance to meet requirements of future QC applications.

In this paper, an S-domain control model for a digitally- controlled dc-dc buck converter is presented. The model gives detailed description about the gain and the phase lag of each block in the control loop in digital implementation. There is a significant phase lag in the digital implementation compared to that of a analog counterpart. This model has been experimentally verified in a field- programmable-gate-array (FPGA) based DC-DC buck converter in the laboratory. The model is easily understandable and practically useful for a majority of power electronic engineers familiar with DC converters using traditional analog control to design a digital compensator. This model can be easily extended to other converter topologies.