With the rise of many-core chips that require substantial bandwidth from the network on chip (NoC), integrated photonic links have been investigated as a promising alternative to traditional electrical interconnects. While numerous opto-electronic NoCs have been proposed, evaluations of photonic architectures have thus-far had to use a number of simplifications, reflecting the need for a modeling tool that accurately captures the tradeoffs for the emerging technology and its impacts on the overall network. In this paper, we present DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks. We explain our modeling framework and perform an energy-driven case study, focusing on electrical technology scaling, photonic parameters, and thermal tuning. Our results show the implications of different technology scenarios and, in particular, the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature.

Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits.

A semianalytical carbon nanotube field-effect transistor (CNFET) model based on the virtual-source model is presented, which includes series resistance, parasitic capacitance, and direct source-to-drain tunneling leakage. The model is calibrated with recent experimental data down to 9-nm gate length. Device performance of 22- to 7-nm technology nodes is analyzed. The results suggest that contact resistance is the key performance limiter for CNFETs; direct source-to-drain tunneling results in significant leakage due to low effective mass in carbon nanotubes and prevents further downscaling of the gate length. The design space that minimizes the gate delay in CNFETs subject to OFF-state leakage current (I_OFF) constraints is explored. Through the optimization of the length of the gate, contact, and extension regions to balance the parasitic effects, the gate delay can be improved by more than 10% at 11- and 7-nm technology nodes compared with the conventional 0.7 × scaling rule, while the OFF-state leakage current remains below 0.5 μA/μm .

A simple analytical FET channel charge partitioning model valid under ballistic and quasi-ballistic transport conditions is developed. With this model, the virtual-source (VS) based charge-based transport compact model is extended to include self-consistent analytical channel charge partitioning models for quasi- and fully-ballistic conditions, with continuous current and charges and their derivatives. Drift-diffusion with or without velocity-saturation transport conditions are also comprehended with adaptations of existing-literature models, and the resulting terminal charges and capacitances are compared with those assuming ballistic operation. With only a limited number of physically meaningful parameters, the extended VS compact model forms an ideal platform for the exploration of the dynamic behavior of current and future FET devices. The simple model is validated here by comparison with experimental data from a well-characterized industry 45-nm metal/high-k complementary metal-oxide-semiconductor including parasitic elements using a Verilog-A implementation to simulate ring oscillators. It is also validated by comparison with S-parameter-derived capacitances of near-ballistic III-V high-electron mobility transistors. In both cases, the effects of different assumed transport conditions on the dynamic device behavior are explored.

In this paper, we study the self-heating mechanism and its impact on electrical performance of short gate length GaN high electron mobility transistors (HEMTs) based on electrothermal TCAD simulations. We propose an equivalent channel temperature to quantify the current degradation due to self-heating and also resolve the discrepancies between temperature measurements through electrical methods and thermal methods in the literature. We then explain the equivalent channel temperature’s behavior using the temperature- and field-dependent electron transport theory for short gate length HEMTs. The implications and guidelines to the various aspects of device design are also discussed.

Parasitic capacitances have become a main issue for advanced technology nodes. In this paper, we develop analytical models for parasitic capacitance components for several device structures, including bulk devices, fully depleted silicon-on-insulator devices, and double-gate devices. With these models, we analyze the impact of parasitic capacitances on the circuit-level performance for logic applications. Si complementary metal-oxide-semiconductor roadmap projection is revisited beyond 32-nm technology, with different device design scenarios examined.