This article proposes a three-dimensional heterogenous-integrated (3DHI) switchable bandpass filter bank with two independent wideband filter channels that cover 26–40 GHz and 32.5–40 GHz, respectively. An accurate wafer-level process with a high hollowed ratio of the applied 8-inch high-resistivity-silicon (HR-Si) interposer wafers is presented to form both compact filter channels. Above the interdigital filter patterns fabricated on the bottom interposer wafer, deep cavities are etched in the cap interposer wafer to improve the quality factor of the filter bank. Besides the cavities, the cap interposer wafer is 35% hollow inside, which two bare dies of GaAs single-pole double-throw (SPDT) switches and two thin film resistors are attached to the bottom interposer after the wafer-to-wafer (W2W) bonding. To ensure good out-of-band performance, a 3D EM co-simulation of the switch layout at the chip level and filter patterns at the package level is applied. Measurement results show that the switchable filter bank achieves a high isolation of 50 dB and a competitive shape factor (BW_30dB/BW_3dB) of about 1.3. In addition, the size of the switchable filter bank is only 7.0 mm × 3.5 mm × 0.6 mm, and the weight is only 0.1 g.

A wideband hybrid envelope tracking supply modulator (HETSM) with a slew-rate-enhanced linear amplifier (LA) is described in this work. The proposed slew-rate enhancement (SRE) structure introduces a parallel auxiliary current path directly to the gate of the class-AB output stage, significantly accelerating the charging and discharging processes of the Miller capacitor without modifying the operating point of the remaining LA. The current delivered via this supplementary path shows a rapid increase, with changes in input voltage, culminating in diminished quiescent current levels. The supply modulator is fabricated in a 180 nm CMOS process. The measurement results show that HETSM is able to track a 100 MHz, 16QAM signal accurately, achieving the maximum efficiency of 87.4% at a 5.12 W output power, with a load that consists of a 5 $\mathsf{\Omega }$ resistor and a paralleled 100 pF capacitor. The proposed LA realizes a slew rate of −1857/+1239 $\mathrm{V}/\mathsf{\mu }\mathrm{s}$ and a bandwidth of 226.6 MHz under a 24 mA quiescent current.

This paper analyzes the common-mode interference conducted by the planar transformer in an isolated DC-DC converter and proposes a scheme for common-mode interference suppression. The scheme integrates the compensation capacitor for suppressing the common-mode current into the planar transformer, and its working principle is briefly explained in the paper. In addition, the scheme is verified by an active clamped forward converter. The application of this scheme in forward converter requires that the filter inductor on the secondary side be placed between the source of MOSFETs and the ground of secondary side, and it is necessary to add an inductor at the feedback terminal of the compensation loop, which needs to be coupled with the secondary filter inductor to ensure the normal driving of the MOSFETs. Finally, we made a prototype with an input voltage of 28 V and an output voltage of 5 V, and tested the common-mode interference of the prototype when using different planar transformers, which verified the feasibility of the scheme proposed in this paper.

High-efficiency and high-power-density point-of-load (POL) converters are critical for data center power supplies. Although hybrid resonant switched-capacitor (ReSC) converters can substantially reduce the volume of passive components, they often suffer from severe efficiency degradation when the switching frequency mismatches the resonant frequency due to component tolerances. To address this challenge, this paper proposes a parameter-mismatch insensitive cascaded POL converter by integrating a BUCK stage with a cascaded voltage divider (CVD). By introducing an auxiliary resonant branch, a multi-resonant operation is established, enabling the residual inductor energy caused by component variations to be transferred to the output during the dead time with virtually eliminated hard-switching losses. Consequently, precise matching between the switching frequency and the resonant frequency is no longer mandatory. A 12 V-to-1 V/30 A GaN-based prototype was developed to validate the theoretical analysis. Experimental results demonstrate that the proposed converter maintains high efficiency under a ±10% component variation and achieves robust voltage regulation and fast transient response, making it highly suitable for high-current data center applications.

This paper proposes a dual−loop model predictive control (MPC) scheme based on grid−side current for modular multilevel converter−based high−voltage direct current (MMC−HVDC) systems. The proposed hybrid control structure combines an MPC−based inner current loop with a PI−based outer voltage loop, designed to enhance dynamic response and steady−state accuracy in HVDC transmission. With the advancement of flexible HVDC technology, modular multilevel converters (MMCs) have been widely adopted due to their excellent scalability and operational flexibility. Model predictive control (MPC), as an advanced control strategy, has demonstrated significant advantages in MMC−HVDC applications. In this study, a dual−loop control system is designed, with MPC as the inner current loop and PI control as the outer voltage loop. This structure effectively enhances control accuracy and ensures system reliability. To validate the effectiveness of the proposed control strategy, a 1000 MW wind power integration MMC−HVDC simulation model was built in Simulink. Simulation results show that the proposed dual−loop MPC strategy can significantly improve control precision and maintain the reliability of the MMC−HVDC system. The proposed strategy is validated through detailed simulations of a 1000 MW wind−integrated MMC−HVDC system, demonstrating superior performance over conventional PI control in terms of overshoot reduction and disturbance rejection.

This paper addresses the capacitor voltage balancing issue of submodules (SMs) in Modular Multilevel Converters (MMCs) operating under low switching frequencies by proposing a voltage balancing control strategy based on dynamic threshold adjustment. First, a dynamic model of SM capacitor voltage in MMCs is established, and the causes of capacitor voltage imbalance are analyzed. Then, based on the coupling relationship between switching frequency and voltage balancing, and the imbalance model under dynamic operating conditions, a dynamic threshold adjustment strategy is designed. A Fuzzy Logic Controller (FLC) is employed to dynamically adjust the voltage imbalance threshold in real time, ensuring capacitor voltage balance while optimizing the switching frequency and reducing system losses. Simulation results show that the proposed strategy can effectively maintain SM capacitor voltage balance under low-switching-frequency conditions, thereby improving system stability.