In this letter, the design and performance of a Ka-band 5-b monolithic microwave integrated circuit phase shifter is presented. In the 180° phase bit, a developed switched-path-type topology is employed in order to extend the bandwidth and achieve good phase shifting characteristics. The fabricated phase shifter demonstrates an rms phase error of less than 4.7° and an rms amplitude error of less than 0.6 dB over the frequency band from 31 to 40 GHz. The input and output return loss is measured to be better than 9 dB, and the chip size is 2.55 mm × 1.3 mm.

The newly discovered “long-term” multicarrier multipactors that can be induced by low-energy electric fields potentially threatens the reliability of spaceborne microwave systems. It also causes a new technical challenge to the prediction of the global occurrence threshold of multicarrier multipactors. In this paper, we propose efficient approaches to rapidly compute the fluctuation of space electrons in the evolving process of a multicarrier multipactor, based on which Monte Carlo approaches are developed to efficiently find the global “worst case” waveforms and the occurrence thresholds for both “single-event” and “long-term” multipactors. The proposed approaches can be used for wideband devices, providing an efficient integrated solution for the multicarrier multipactor analysis for practical high-power microwave devices with inhomogeneous field distribution.

This paper demonstrated the design and fabrication of a TR microsystem in Ka-band based on silicon 3D Heterogeneous-integration. To achieve this microsystem, we proposed a novel silicon interposer with bonded metal on RDL, which solved the compatibility problem involved in eutectic bond and wirebond processes. A brand new temperature-gradient-free stacking method achieved by printing conductive adhesive bonding technology is also presented, which reduces the stacking temperature while introduces no extra temperature-gradient. Based on these technologies, a 4-channels T/R microsystem with 6-bits phase for both T/R channels, smaller than 9.5mm×9.8mm×2mm, lighter than 0.3g and working at 33-35GHz is fabricated, whose receive noise figure is lower than 5.7dB and the maximum output power exceeds 25dBm.

The amplitude and phase imbalances of the in-phase (I) and quadrature (Q) branches inherent in the direct conversion receiver structure cause the generation of image frequency interference signals. In this paper, a frequency-domain I/Q imbalance calibration algorithm is proposed for wideband direct conversion receivers. The I/Q imbalance model is rebuilt by applying the infinitesimal method and FFT algorithm. The mathematical expressions for the exact computation of the I/Q imbalance parameters are derived based on the frequency-domain statistical properties of the baseband signal. The two phase parameters, frequency-dependent I/Q imbalance (FD-IQI) and frequency-independent I/Q imbalance (FI-IQI), are separated according to the parity properties of the imbalance parameter. To avoid the interference from the transmitter, the receiver impairment estimation is performed using a frequency offset (FO) DC training signal, and a low-cost real-valued compensation (RVC) filter is introduced to correct the impairments of the received signal. The performances of the proposed calibration model are evaluated through simulations and experiments. The simulation results show that the image rejection ratio (IRR) is improved to 80-120 dBc and can also exceed 40 dBc at high noise levels. The experimental results based on the CX9261A evaluation board show that the average IRR of the multi-tone signal is increased by 24.99 dB, and the IRR of the wideband signal is increased by 19.08 dB.

Based on the 0.5 μm GaAs enhancement/depletion (E/D) Pseudomorphic High Electron Mobility Transistor (pHEMT) process, a 7.5–9 GHz two-channel amplitude phase control multi-function chip (MFC) was developed successfully. The chip was integrated with a 6-bit digital phase shifter, a 6-bit digital attenuator, and a single pole single throw (SPST) switch in each channel. A design for the absorptive SPST switch is deployed to optimize the return loss and control channel array calibration. In the 8 dB and 16 dB attenuation bit, a switched-path-type topology is employed in order to obtain a good flatness of attenuation characteristic and achieve low additive phase shift. A 27-bit serial-to-parallel converter (SPC) was introduced to decrease the control lines and pads of the chip, and the power consumption was less than 70 mW. The measurement result shows that the insertion loss is less than −13 dB and the return loss is better than −19 dB. In both channels, the 64-state root mean square (RMS) errors of the phase shifter is less than 2° and the RMS parasitic amplitude error is less than 0.2 dB. The RMS attenuation error is less than 0.45 dB and the RMS parasitic phase error is less than 2.4°. The size of the chip is 3.5 mm × 4.5 mm.

This brief presents an X/Ku concurrent dual-wideband power amplifier (PA) monolithic microwave integrated circuit (MMIC) fabricated with 0.25lm GaN-on-SiC technology. The input matching network (IMN) and output matching network (OMN) of the proposed PA are designed based on electric and magnetic coupled symmetric multi-resonator matching networks (MRMNs) respectively to obtain four reflection zeros. Through symmetrical network analysis method, the four reflection zeros of the matching network are equally divided into two sub frequency bands and an optimal dual-wideband matching performance is realized. The proposed PA obtains average saturated output power of 36.9dBm and 35.9dBm in 9GHz-10GHz and 13.5GHz-16GHz. The measured average power-added efficiency (PAE) are 34.8% and 32.6% in 9GHz-10GHz and 13.5GHz-16GHz.