Although two-terminal perovskite-silicon tandem solar cells have rapidly increased in efficiency, they have only been demonstrated with n-type silicon, which currently constitutes less than 5% of the global photovoltaics market. In this paper, we realize the first two-terminal perovskite tandem with p-type silicon by developing a recombination contact that enables voltage addition without damaging either subcell. We find that silicon interband recombination contacts are limited by a $\text{SiO}_{x}$ charge-extraction barrier, which forms during oxidative top-cell fabrication. A sputtered 30-nm indium tin oxide layer is found to protect the silicon cell surface from oxidation, while forming a recombination contact with the p-type nickel oxide hole transport layer for the perovskite top cell. Using this recombination contact we achieve voltage addition between the perovskite top cell and aluminum back-surface field p-type silicon bottom cell. We also find that minimizing moisture on the nickel oxide surface is important for achieving a stable open-circuit voltage under illumination. The recombination contact developed herein could play an important role in near-future developments.

Potential‐induced degradation (PID) is an important reliability issue of photovoltaic modules. For future field applications of perovskite photovoltaic modules, it is important to study the PID behavior under real‐world operating conditions, which has not yet been thoroughly researched. This work presents PID investigation of glass‐encapsulated perovskite solar cells (PSCs) at different stress conditions for an extended duration of 55 h. At room condition (25 °C, 20% relative humidity [RH]) the efficiency is reduced by 59% when −1000 V is applied to the short‐circuited PSCs, whereas under elevated stress condition (60 °C, 60% RH) the device efficiency suffers severe degradation of >90%. The PID effects are analyzed with several characterization methods, revealing that Na⁺ion migration from the front glass pane toward the perovskite layer causes the degradation. Application of a reverse voltage bias right after PID results in very poor recovery under elevated condition compared to the recovery of devices under room condition. It is proposed that PID and its recovery rate depend on the external stress conditions and the reverse bias strategy is not sufficient for the recovery. Possible mitigation strategies which can open a new avenue for further research on PID in PSCs are also presented.