Structural health monitoring (SHM) systems are used to analyze the health of infrastructures such as bridges, using data from various types of sensors. While SHM systems consist of various stages, feature extraction and pattern recognition steps are the most important. Consequently, signal processing techniques in the feature extraction stage and machine learning algorithms in the pattern recognition stage play an effective role in analyzing the health of bridges. In other words, there exists a plethora of signal processing techniques and machine learning algorithms, and the selection of the appropriate technique/algorithm is guided by the limitations of each technique/algorithm. The selection also depends on the requirements of SHM in terms of damage identification level and operating conditions. This has provided the motivation to conduct a Systematic literature review (SLR) of feature extraction techniques and pattern recognition algorithms for the structural health monitoring of bridges. The existing literature reviews describe the current trends in the field with different focus aspects. However, a systematic literature review that presents an in-depth comparative study of different applications of machine learning algorithms in the field of SHM of bridges does not exist. Furthermore, there is a lack of analytical studies that investigate the SHM systems in terms of several design considerations including feature extraction techniques, analytical approaches (classification/ regression), operational functionality levels (diagnosis/prognosis) and system implementation techniques (data-driven/model-based). Consequently, this paper identifies 45 recent research practices (during 2016–2023), pertaining to feature extraction techniques and pattern recognition algorithms in SHM for bridges through an SLR process. First, the identified research studies are classified into three different categories: supervised learning algorithms, neural networks and a combination of both. Subsequently, an in-depth analysis of various machine learning algorithms is performed in each category. Moreover, the analysis of selected research studies (total = 45) in terms of feature extraction techniques is made, and 25 different techniques are identified. Furthermore, this article also explores other design considerations like analytical approaches in the pattern recognition process, operational functionality and system implementation. It is expected that the outcomes of this research may facilitate the researchers and practitioners of the domain during the selection of appropriate feature extraction techniques, machine learning algorithms and other design considerations according to the SHM system requirements.

To perform a comprehensive assessment of important infrastructures (like bridges), the process of structural health monitoring (SHM) is employed. The development and implementation of SHM systems are generally based on wireless sensor networks (WSN) platforms. However, most of the WSN platforms are battery-powered, and therefore, have a limited battery lifetime. The power constraint is generally addressed by applying energy harvesting (EH) technologies. As a result, there exists a plethora of WSN platforms and EH techniques. The employment of a particular platform and technique are important factors during the development and implementation of SHM systems and depend upon various operating conditions. Therefore, there is a need to perform a systematic literature review (SLR) for WSN platforms and EH techniques in the context of SHM for bridges. Although state-of-the-art review articles present multiple angles of the field, there is a lack of an SLR presenting an in-depth comparative study of different WSN platforms and EH techniques. Moreover, a systematic analysis is also needed for the exploration of other design considerations such as inspection scale (global/local), response type (static/dynamic), and types of sensors. As a result, this SLR selects 46 articles (during 2007–2023), related to EH techniques and WSN platforms in SHM for bridges. The selected articles are classified into three groups: WSN platforms, energy harvesting techniques, and a combination of both. Subsequently, a comparative analysis of WSN platforms and EH techniques is made. Furthermore, the selected articles (total = 46) are also explored in terms of sensor type, inspection scale, and response type. As a result, 17 different sensor types are identified. This research is significant as it may facilitate the various stakeholders of the domain during the selection of appropriate WSN platforms, EH techniques, and related design issues.

Bridges are critical to national mobility and economic flow, making dependable structural health monitoring (SHM) systems essential for safety and durability. However, the SHM data quality is often affected by sensor faults, transmission noise, and environmental interference. To address these issues, anomaly detection methods are widely adopted. Despite their wide use and variety, there is a lack of systematic evaluation that comprehensively compares these techniques. Existing reviews are often constrained by limited scope, minimal comparative synthesis, and insufficient focus on real-time performance and multivariate analysis. Consequently, this systematic literature review (SLR) analyzes 36 peer-reviewed studies published between 2020 and 2025, sourced from eight reputable databases. Unlike prior reviews, this work presents a novel four-dimensional taxonomy covering real-time capability, multivariate support, analysis domain, and detection methods. Moreover, detection methods are further classified into three categories: distance-based, predictive, and image processing. A comparative evaluation of the reviewed detection methods is performed across five key dimensions: robustness, scalability, real-world deployment feasibility, interpretability, and data dependency. Findings reveal that image-processing methods are the most frequently applied (22 studies), providing high detection accuracy but facing scalability challenges due to computational intensity. Predictive models offer a trade-off between interpretability and performance, whereas distance-based methods remain less common due to their sensitivity to dimensionality and environmental factors. Notably, only 11 studies support real-time anomaly detection, and multivariate analysis is often overlooked. Moreover, time-domain signal processing dominates the field, while frequency and time-frequency domain methods remain rare despite their potential. Finally, this review highlights key challenges such as scalability, interpretability, robustness, and practicality of current models. Further research should focus on developing adaptive and interpretable anomaly detection frameworks that are efficient enough for real-world SHM deployment. These models should combine multi-modal strategies, handle uncertainty, and follow standardized evaluation protocols across varied monitoring environments.

This article has proposed an efficient area-optimized elliptic curve cryptographic processor architecture over $GF\left(2^{409}\right)$ and $GF\left(2^{571}\right)$. The proposed architecture employs Lopez-Dahab projective point arithmetic operations. To do this, a hybrid Karatsuba multiplier of 4-split polynomials is proposed. The proposed multiplier uses general Karatsuba and traditional schoolbook multiplication approaches. Moreover, the multiplier resources are reused to implement the modular squares and addition chains of the Itoh-Tsujii algorithm for inverse computations. The reuse of resources reduces the overall area requirements. The implementation is performed in Verilog (HDL). The achieved results are provided on Xilinx Virtex 7 device. In addition, the performance of the proposed design is evaluated on ASIC 65 nm process technology. Consequently, a figure-of-merit is constructed to compare the FPGA and ASIC implementations. An exhaustive comparison to existing designs in the literature shows that the proposed architecture utilizes less area. Therefore, the proposed design is the right choice for area-constrained cryptographic applications.

Lattice-based post-quantum cryptography (PQC) algorithms demand number theoretic transform (NTT)-based polynomial multiplications. NTT-based polynomials’ multiplication relies on the computation of forward number theoretic transform (FNTT) and inverse number theoretic transform (INTT), respectively. Therefore, this work presents a unified NTT hardware accelerator architecture to facilitate the polynomial multiplications of the CRYSTALS-Kyber PQC algorithm. Moreover, a unified butterfly unit design of Cooley–Tukey and Gentleman–Sande configurations is proposed to implement the FNTT and INTT operations using one adder, one multiplier, and one subtractor, sharing four routing multiplexers and one Barrett-based modular reduction unit. The critical path of the proposed butterfly unit is minimized using pipelining. An efficient controller is implemented for control functionalities. The simulation results after the post-place and -route step are provided on Xilinx Virtex-6 and Virtex-7 field-programmable gate array devices. Also, the proposed design is physically implemented for validation on Virtex-7 FPGA. The number of slices utilized on Virtex-6 and Virtex-7 devices is 398 and 312, the required number of clock cycles for one set of FNTT and INTT computations is 1410 and 1540, and the maximum operating frequency is 256 and 290 MHz, respectively. The average figure of merit (FoM), where FoM is the ratio of throughput to slices, illustrates 62% better performance than the most relevant NTT design from the literature.

The focus of this article is to present a novel crypto-accelerator architecture for a resource-constrained embedded system that utilizes elliptic curve cryptography (ECC). The architecture is built around Binary Edwards curves (BEC) to provide resistance against simple power analysis (SPA) attacks. Furthermore, the proposed architecture incorporates several optimizations to achieve efficient hardware resource utilization for the point multiplication process over $GF\left(2^m\right)$. This includes the use of a Montgomery radix-2 multiplier and the projective coordinate hybrid algorithm (combination of Montgomery ladder and double and add algorithm) for scalar multiplication. A two-stage pipelined architecture is employed to enhance throughput. The design is modeled in Verilog HDL and verified using Vivado and ISE design suites from Xilinx. The obtained results demonstrate that the proposed BEC accelerator offers significant performance improvements compared to existing solutions. The obtained throughput over area ratio for $GF\left(2^{233}\right)$ on Virtex-4, Virtex-5, Virtex-6, and Virtex-7 Xilinx FPGAs are 9.43, 14.39, 26.14, and 28.79, respectively. The computation time required for a single point multiplication operation on the Virtex-7 device is 19.61 µs. These findings indicate that the proposed architecture has the potential to address the challenges posed by resource-constrained embedded systems that require high throughput and efficient use of available resources.