Digital image compression is applied to reduce camera bandwidth and storage requirements, but real-time lossless compression on a high-speed high-resolution camera is a challenging task. The article presents hardware implementation of a Bayer colour filter array lossless image compression algorithm on an FPGA-based camera. The compression algorithm reduces colour and spatial redundancy and employs Golomb–Rice entropy coding. A rule limiting the maximum code length is introduced for the edge cases. The proposed algorithm is based on integer operators for efficient hardware implementation. The algorithm is first verified as a C++ model and later implemented on AMD-Xilinx Zynq UltraScale+ device using VHDL. An effective tree-like pipeline structure is proposed to concatenate codes of compressed pixel data to generate a bitstream representing data of 16 parallel pixels. The proposed parallel compression achieves up to 56% reduction in image size for high-resolution images. Pipelined implementation without any state machine ensures operating frequencies up to 320 MHz. Parallelised operation on 16 pixels effectively increases data throughput to 40 Gbit/s while keeping the total memory requirements low due to real-time processing.

Hardware description languages and tools require a considerable amount of teaching activities in a digital systems design course, which is difficult to accommodate in a limited time frame, and to use for e-learning. This paper presents our user-friendly and open-source web-based digital design tool, SHDL, which is used to describe and simulate hardware components and translate them into a standard language. SHDL is a teaching language and tool for digital design, which aims to improve the teaching and learning experience in digital systems design courses. The use and evaluation of the proposed online teaching model for the Digital Electronic Systems Design (DESD) course, using the SHDL tool for e-learning during the COVID-19 phase, is presented. Using the SHDL language and web tool, we have created many examples of digital circuits that prepare students to explore their own designs. The example components can also be used as digital system modules, leading to better modularity of the final project. The use of SHDL in the DESD course has shown that the proposed language leads to fewer syntax, simulation and synthesis errors in the designed circuits. The evaluation results show that at the end of the laboratory exercises, there was no longer a difference in knowledge between the students without prior VHDL experience and the other students. The results encourage us to continue using SHDL, and to complement the traditional DESD teaching methods with e-learning.

This paper presents the development of a ship-detecting edge-processing system for deployment on an aerial FPGA platform. A ship detection chain was developed with imager-specific pre-processing algorithms, massively parallel FPGA neural network inference, and host post-processing procedures. The ship detection binary neural network implemented in combinational logic enables high frame and detection rates, and achieves 98.40% patch classification accuracy. A new algorithm for optimizing a combinational binary neural network circuit is presented that merges multiple neurons in a network layer taking advantage of similarities between neuron weights, which leads to lower logic size and power consumption. Thus, state-of-the-art performance is achieved in comparison to similar previous works using combinational binary neural networks, achieving 38 ns inference latency, 0.425 W of power dissipation, and only 19 k FPGA slices.

Design of a video processing circuit requires extensive understanding of digital systems and image processing algorithms. A typical design process involves different tools and languages, which make the task difficult for undergraduate students. We present a teaching method using a web-based tool for initial algorithm study and test bench design. The algorithm is later described in a high-level language, optimised and implemented on a custom programmable logic platform.

Digital image compression is applied to reduce camera bandwidth and storage requirements, but real-time lossless compression on a high-speed high-resolution camera is a challenging task. The article presents hardware implementation of a Bayer colour filter array lossless image compression algorithm on an FPGA-based camera. The compression algorithm reduces colour and spatial redundancy and employs Golomb-Rice entropy coding. A rule limiting the maximum code length is introduced for the edge cases. The proposed algorithm is based on integer operators for efficient hardware implementation. The algorithm is first verified as a C++ model and later implemented on Xillinx Zynq UltraScale+ device using VHDL. An effective tree-like pipeline structure is proposed to concatenate codes of compressed pixel data to generate a bitstream representing data of 16 parallel pixels. The proposed parallel compression achieves up to 56% reduction in image size for high resolution images. Pipelined implementation without any state machine ensures operating frequencies up to 320 MHz. Parallelised operation on 16 pixels effectively increases data throughput to 40 Gbit/s while keeping total memory requirements low due to real-time processing.