This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.

True random number generators (TRNGs) play an important role in encryption systems. In this brief, a novel method of generating true random numbers on a field-programmable gate array (FPGA) is proposed based on the random jitter of a multi-stage feedback ring oscillator (MSFRO) as the entropy source. Based on the traditional ring oscillator, a multi-stage feedback structure is added to enlarge the range of clock jitter, and improve the frequency of clock sampling and the randomness of the entropy source. Different from the traditional clock sampling structure, we use the clock jitter signal generated by the MSFRO to sample the clock signal generated by the phase-locked loop (PLL) of the FPGA. The obtained output value is operated by XOR to reduce the deviation of the output value and improve its randomness. The TRNG is implemented in Xilinx Virtex-6 FPGA, which has low hardware resource consumption and high throughput. The entropy source classification, hardware resources and throughput are compared with those of existing TRNGs. The results showed that the proposed TRNG only consumed 24 LUTs and 2 DFFs. Compared with other TRNGs, this design has very low hardware resource consumption and its throughput is up to 290 Mbps. The random bit sequence generated by this TRNG passes the NIST SP800-22 test and the NIST SP800-90B test.

This paper presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs.

True random number generators (TRNGs) perform an irreplaceable role in securing information systems. In this brief, a lightweight hybrid entropy source TRNG implementation scheme based on jitter and metastability is proposed, which uses the underlying field programmable gate array (FPGA) primitive language to construct a dual cross-coupled XOR gate (DCCX) unit to generate a random output sequence and is deployed by automatic layout and routing with the Xilinx compiler. The experimental results show that the generated random sequence passes the NIST SP800-22 test, the TESTU01 test and the AIS-31 test. The structure has been extensively tested under voltage and temperature variations and shows excellent robustness. It is worth mentioning that the proposed TRNG consumes only 12 LUTs and 10 DFFs, and achieves 150Mbps and 200Mbps throughput on Xilinx Artix-7 and Kintex-7 FPGAs, respectively, which shows a highly efficient resource utilization compared to the previously published TRNGs.