We present an open-source deep artificial neural network (ANN) model for the accelerated design of polarization-insensitive subwavelength grating (SWG) couplers on the silicon-on-insulator platform. Our model can optimize SWG-based grating couplers for a single fundamental-order polarization, or both, by splitting them counter-directionally at the grating level. Alternating SWG sections are adopted to reduce the reflections (loss) of standard, single-etch devices-further accelerating the design time by eliminating the need to process a second etch. The model of this device is trained by a dense uniform dataset of finite-difference time-domain (FDTD) optical simulations. Our approach requires the FDTD simulations to be made up front, where the resulting ANN model is made openly available for the rapid, software-free design of future standard photonic devices, which may require slightly different design parameters (e.g., fiber angle, center wavelength, polarization) for their specific application. By transforming the nonlinear input-output relationship of the device into a matrix of learned weights, a set of simple linear algebraic and nonlinear activation calculations can be made to predict the device outputs 1,830 times faster than numerical simulations, within 93.2% accuracy of the simulations.

We present a CMOS-compatible optoelectronic directed logic architecture that achieves high computational throughput (number of operations per second per unit area) by its ultracompact form factor. High speed-to-power performance is also achieved, by the low capacitance and high junction-to-mode overlap of low-radii SOI vertical pn junction microdisk switches. By using wavelength-division multiplexing and two electrical control signals per disk, each switch performs (N)OR, (N)AND, and X(N)OR operations simultaneously. Connecting multiple switches together, we demonstrate higher-order scalability in five fundamental N-bit logic circuits: AND/OR gates, adders, comparators, encoders, and decoders. To the best of our knowledge, these circuits achieve the lowest footprint of silicon-based multigigabit-per-second optical logic devices in literature.

We experimentally demonstrate, to the best of our knowledge, the first microdisk-based silicon-photonic mode-division (de)multiplexer circuit, which is compatible with wavelength-division multiplexing for high aggregate bandwidth on-chip optical communications. This circuit uses waveguide-wrapped microdisk resonators, featuring low levels of intermodal crosstalk and insertion loss within an ultracompact footprint. In addition, the proposed device presents an increased free spectral range, allowing for 530 combined data channels. Furthermore, the microdisk structure naturally supports vertically oriented depletion-type pn junctions, which have been shown to reach subfemtojoule-per-bit modulation efficiencies. The high modulation efficiency, compactness, and wide free spectral range of waveguide-wrapped microdisk resonators present the potential for higher bandwidth and lower energy consumption in next-generation data processing and communication applications.

We propose a U-shaped pn junction in a silicon-on-insulator microdisk resonator to effectively double the junction–mode overlap in the state-of-the-art, vertical pn junction microdisk electro-optical (EO) modulators. The U-shaped pn junction promotes the maximum overlap between the junction depletion zone and the whispering gallery optical mode in the microdisk. By fully depleting the p region of the npn-sequenced U-junction, the capacitance is reduced below 3 fF, which significantly improves the speed and power performance. In this work, we implement the high-efficiency, depleted U-junction design to maximize the operating bandwidth of EO modulators, EO logic elements, EO 2 × 2 switches for wavelength-division cross-connects, 2 × 2 reconfigurable optical add–drop multiplexers, optical-to-electrical-to-optical (OEO) repeaters-with-gain, OEO wavelength converters, and 2 × 2 optical–optical logic gates. These devices all operate in the 7.6-to-50 GHz bandwidth range with ultralow energy consumption between 0.4 and 9.8 fJ/bit. By using CMOS-compatible materials and fabrication-feasible design dimensions, our proposed high-performance devices offer a promising potential in next-generation, high-volume electro-optical communications and computing circuits.