The peculiar properties of the gapless surface states with a Dirac cone shaped energy dispersion in topological insulators (TIs) enable promising applications in photodetection with an ultra-broad band and polarization sensitivity. Since many TIs can be easily grown on silicon (Si) substrates, TIs on Si could make an alternative route for photon detection of Si photonics. We present good device performances of a Si-based single-crystal bismuth telluride (Bi₂Te₃) photoconductive detector. Room temperature photo responses to 1064 nm and 1550 nm light illumination were demonstrated. Linear dependences of the photocurrent on both the incident light power and the bias voltage were observed. The main device parameters including responsivity and quantum efficiency were extracted.

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits.

We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.

GeSn alloy with 7.68% Sn concentration grown by molecular beam epitaxy has been rapidly annealed at different temperatures from 300°C to 800°C. Surface morphology and roughness annealed below or equal to 500°C for 1 min have no obvious changes, while the strain relaxation rate increasing. When the annealing temperature is above or equal to 600°C, significant changes occur in surface morphology and roughness, and Sn precipitation is observed at 700°C. The structural properties are analyzed by reciprocal space mapping in the symmetric (004) and asymmetric (224) planes by high resolution X-ray diffraction. The lateral correlation length and the mosaic spread are extracted for the epi-layer peaks in the asymmetric (224) diffraction. The most suitable annealing temperature to improve both the GeSn lattice quality and relaxation rate is about 500°C.