Asymmetrical dual three-phase (ADTP) multiphase arrangements are becoming increasingly important for powertrain applications within the automotive sector. However, further research and development should be carried out in order to improve these arrangements. Lately, there has been a growing interest in exploring enhancements for the pulse-width modulation (PWM) techniques aimed at reducing the current stress of the propulsion system’s DC-Link. In electric vehicle (EV) applications, the voltage-source inverter (VSI) must deliver high power density while meeting stringent reliability requirements. A critical component within the VSI is the DC-Link capacitor, which occupies up to 40% of the inverter volume and contributes to approximately 30% of power converter failures. Reducing the DC-Link ripple current can significantly enhance reliability and reduce system size. However, improvements on the input side often come at the expense of the output side, where excessive current ripple increases Joule losses and induces torque ripple, leading to mechanical vibrations and reduced motor efficiency. Addressing this trade-off is particularly important in ADTP systems, as these configurations are increasingly adopted for high-density, fault-tolerant propulsion systems. In this context, this work evaluates the most relevant carrier-based (CB)PWMtechniques regarding the output current ripple quality of an ADTP. For this purpose, a novel method is proposed to calculate the harmonic distortion factor (HDF) of an ADTP arrangement. It is based on the double Fourier integral formalism, instead of the conventional time-domain analysis. The method developed in this work provides accurate harmonic profiles for a thorough comparison among CB-PWMs and enhances the theoretical understanding of how harmonic cancellation works. This innovative approach not only makes the results insensitive to simulation time resolution but also effectively mitigates errors and offsets that arise over the time-domain integration of the voltage measurement. This type of analysis is particularly meaningful when examining the interleaved variations of these CB-PWMs, as they focus on harmonic reduction or cancellation. The experimental validation of this method demonstrates that the results are consistent, providing confidence in the theoretical analysis. In this sense, this work determines how the interleaving schemes, typically used to benefit the DC-Link capacitor, affect the HDF of the ADTP arrangements. Furthermore, this study points out which PWM technique is most promising for ADTP-based propulsion systems, for both improving the performance of the powertrain input (DC side) and its output (AC side, i.e. VSI + electric machine), thus helping engineers and researchers in this field.

The DC-Link capacitor plays a crucial role as far as power density and reliability are concerned: it occupies approximately 40% of the inverter, and causes approximately 30% of its failures. Asymmetrical dual three-phase (ADTP) multiphase arrangements are gaining relevance in the automotive sector for powertrain applications. This work focuses on reducing the impact that the widely used double zero sequence injection (DZSI) family of PWM techniques have on such a bulky and failure-prone component in an ADTP arrangement by means of interleaving techniques. By using the double Fourier integral formalism, the input current spectra and the overall performance of these PWM techniques have been derived, in terms of current rms value and voltage ripple in the DC-Link capacitor. Simulations have shown that choosing an adequate interleaving scheme and angle considerably relieves both current and voltage stresses on the DC-Link capacitor compared to noninterleaved operation. Reductions of 84% current rms and 86% voltage ripple have been achieved at static operating points. Finally, by averaging the rms current over WLTP standard driving cycle, reductions up to 26% have been obtained under more realistic conditions. All this would enhance the reliability and reduce the size of the onboard capacitors in future electric vehicles.

In electric drive systems, common-mode voltage (CMV) fluctuations cause bearing currents that damage the motor, deteriorate stator winding insulation, and generate electromagnetic interference (EMI) throughout the system. Several methods have been proposed to mitigate this stray voltage, especially in electric vehicles, where reliability requirements are increasingly stringent. At the same time, improving efficiency—by minimizing power losses—is essential to enhance driving range and thermal management. This article presents a novel two-level three-phase inverter topology combined with hybrid modulation techniques for electric vehicle propulsion systems. The proposed architecture aims to significantly reduce CMV variations while maintaining high overall efficiency. Simulation and experimental results confirm that, depending on the specific operating condition, the proposed solution achieves reductions of more than 80% in CMV fluctuations compared with standard space vector-pulsewidth modulation (SV PWM) operation, efficiency improvements between 0.6% and 1.5% relative to a conventional voltage-source inverter (VSI), and a redistribution of switching losses that can reduce the power dissipated per main VSI device by more than 25%. Unlike previously proposed alternatives, the converter preserves full compatibility with standard VSI control schemes and achieves a superior balance between reliability, CMV mitigation, and efficiency. Therefore, it represents a feasible and promising alternative for future electric vehicle drive systems.