The industry and academia are focusing their efforts on finding more efficient and reliable electrical machines and motor drives. However, many of the motors driven by pulse-width modulated converters face the recurring problem of common-mode voltage (CMV). In fact, this voltage leads to other problems such as bearing breakdown, deterioration of the stator winding insulation and electromagnetic interferences (EMI) that can affect the lifespan and correct operation of the motors. In this sense, multilevel converters have proven to be a useful tool for solving these problems and mitigating CMV over the past few decades. Among other reasons, because they provide additional degrees of freedom when comparing with two-level converters. However, although there are several proposals in the scientific literature on this topic, no complete information has been reviewed about the CMV issues and the different multilevel alternatives that can be used to solve it. In this context, the objective of this work is to determine how multilevel power converters provide additional degrees of freedom to make the reduction of the CMV possible by using specific modulation techniques, making it easier for engineers and scientists in this field to find solutions to this problem. This document consists of a descriptive study that collects the strengths and weaknesses of most important multilevel power converters, with special emphasis on how CMV affects each of them. In addition, the differences of modulation techniques aimed to the CMV reduction are explained in terms of output voltage, operating linear range, and generated CMV. Considering this last, it is recommended to use those modulation techniques that allow the generation of CMV levels of 0 V in order to be able to completely eliminate said voltage.

Neutral point voltage control converters (NPVCC) are being considered for AC drive applications, where their additional degree of freedom can be used for different purposes, such as fault tolerance or common mode voltage (CMV) reduction. For every PWM-driven converter, the CMV is an issue that must be considered since it can lead to shaft voltages between rotor and stator windings, generating bearing currents that accelerate bearing degradation, and can also produce a high level of electromagnetic interference (EMI). In light of these considerations, in this paper a three-dimensional reduced common mode voltage PWM (3D RCMV-PWM) technique is proposed which effectively reduces CMV in five-phase six-leg NPVCCs. The mathematical description of both the converter and the modulation technique, in space-vector and carrier-based approaches, is included. Furthermore, the simulation and experimental analysis validate the CMV reduction capability in addition to the good behaviour in terms of the efficiency and harmonic distortion of the proposed RCMV-PWM algorithm.

One of the most common issues in inverters are open-circuit faults (OPF). In this scenario, a proper fault-tolerant technique must be used to improve the motor performance. Although basic fault-tolerant modulation techniques are normally preferred, this paper proposes a discontinuous pulse-width modulation algorithm (HD-PWM) to operate five-phase inverters under a single OPF. In particular, loss equalization between the remaining switches after a fault occurs is the main objective of the HD-PWM algorithm, thus preventing future faults from occurring. The efficiency and harmonic distortion of the proposed technique are compared to the well-known sinusoidal PWM by simulation and experimentation under OPF conditions. The results obtained show a great performance of the proposed modulation technique, obtaining a relevant efficiency improvement.

Wide Bandgap (WBG) transistors provide better switching performance and higher operating temperatures compared to state of the art Si devices and are suited for high frequency applications due to very short switching times. The main obstacle for implementation of WBG transistors at full potential is the high frequency oscillation in voltage and current during switching transients. Oscillations arise from resonance due to parasitic and device inductances and capacitances. Introduction of WBG transistors depends on the elimination of these oscillations and their negative effect on the performance of power converters. Good layout practice is mandatory, but there is a limit to the reduction of these parasitics and, often, slowing of the semiconductor switching time must be applied. This paper presents a simple methodology for the attenuation of the negative effects of WBG transistor high frequency oscillations without increasing rise and fall times. The proposed methodology is based on determination of the source of feedback resonant frequency between gate and power loops using network analyzer measurement on PCB and utilization of tuned RLC filter. Experimental application of the methodology shows direct relationship between loop resonant frequency and voltage and current oscillations. The proposed method reduces power losses, high frequency oscillations and EMI.

In some power electronic applications, with high current and voltage ranges, discrete devices are not enough unless parallelization techniques are employed. IGBTs are one of the most common and widespread power electronic semiconductors, to make a parallel design with them, either as a discrete devices, dies, individual cells or power modules, it is necessary to know their static and dynamic behaviour. Besides, operation temperature, device parameter tolerances, driver circuit and power layout, as well as different parasitic inductance also affect its performance. The objective of this article is to show and model how all the aforementioned parameters affect the behaviour and performance of a parallelized IGBT, and highlight the design keys for a successful parallelized design.