This work shows the voltage regulation of a DC–DC buck converter by applying sliding mode control using three different cases of sliding surfaces. The DC–DC buck converter is modeled by ordinary differential equations (ODEs) that are solved by applying numerical methods. The ODEs describe two state variables that are associated to the capacitor voltage and the inductor current. The state variable associated to voltage is regulated by applying two well-known sliding surfaces and a third one that is introduced herein to improve the response of the sliding mode control. The stability of the proposed sliding surface is verified by using a Lyapunov theorem to guarantee closed-loop stability. Finally, simulation results show the improvement of voltage regulation when applying the proposed sliding surface compared to already reported approaches.

DC–DC buck converters have been designed by incorporating different control stages to drive the switches. Among the most commonly used controllers, the sliding mode control (SMC) and proportional-integral-derivative (PID) controller have shown advantages in accomplishing fast slew rate, reducing settling time and mitigating overshoot. The proposed work introduces the implementation of both SMC and PID controllers by using the field-programmable gate array (FPGA) device. The FPGA is chosen to exploit its main advantage for fast verification and prototyping of the controllers. In this manner, a DC–DC buck converter is emulated on an FPGA by applying an explicit multi-step numerical method. The SMC controller is synthesized into the FPGA by using a signum function, and the PID is synthesized by applying the difference quotient method to approximate the derivative action, and the second-order Adams–Bashforth method to approximate the integral action. The FPGA synthesis of the converter and controllers is performed by designing digital blocks using computer arithmetic of 32 and 64 bits, in fixed-point format. The experimental results are shown on an oscilloscope by using a digital-to-analog converter to observe the voltage regulation generated by the SMC and PID controllers on the DC–DC buck converter.

This paper presents the theoretical and practical considerations to construct a DC-DC buck converter for low-power applications. The control law is based on the sliding-mode control theory that fits the physical behavior of the DC-DC converter. The experimental results show that is possible to construct a simple control by monitoring one of the circuit state variables (voltage on the capacitor). The sliding-mode control helps to drive the output DC value in spite of the circuit variations and load conditions. The experimental results show a reliable regulated voltage of 3.3 V and 4.3 V with a 125kHz reference frequency.

This paper presents an integrated specification-driven analytical methodology for the design and practical implementation of cascade-controlled Boost DC–DC converters using integer-order and fractional-order lead–lag compensators. Unlike empirical tuning and optimization-based approaches, the proposed framework derives the controller parameters analytically from prescribed transient- and steady-state-performance requirements and, for the fractional-order lead–lag (FO–LL) controller, explicitly incorporates the control-effort level as an additional design specification. The methodology integrates converter sizing, averaged small-signal modeling, controller synthesis, rational approximation of fractional-order dynamics, electronic realization, and software-assisted verification within a reproducible workflow implemented in MATLAB, Simulink, and Simscape. The methodology is first evaluated using a numerical assessment case that examines sensitivity to the fractional approximation order, operation away from the nominal point, converter-parameter variations, controller-component tolerances, and load disturbances. Practical feasibility is then demonstrated using a separate experimental implementation case based on a second Boost converter with a hybrid IO–LL/FO–LL cascade configuration, evaluated through three validation levels—block-level simulation, switching circuit-level simulation, and experimental evaluation. The circuit-level and experimental evaluations exhibit consistent transient behavior under their respective test conditions, with representative overshoots of 5.02% and 4.2%, respectively, while the experimental prototype maintains a steady-state error of approximately 1% and achieves approximately 91% conversion efficiency. Overall, the results demonstrate that the proposed methodology provides a systematic and reproducible path from performance specifications to practical controller realization while retaining stable operation and implementation-oriented control effort under the evaluated modeling, operating, and hardware variations.