The paper presents a proposal for capacitance and inductance selection procedure of the modular multilevel converter. Two analysis criteria are taken into consideration, the circulating current and voltage ripple across submodule capacitors. Results are obtained numerically by using the converter averaged model based on state equations. In the modular multilevel converter operating under a direct modulation method, based on sinusoidal modulating signals, circulating currents flows through the converter arms. These currents are strongly dependant on the component parameters of the converter, such as: submodule DC-link capacitor capacitance and arm inductor inductance. Both components form a series resonance circuit in each converter arm. Resonance that occurs in the converter arm has to be avoided and therefore it is important to properly select component parameters while taking into account all possible resonances. Such components selection should be carried out at an early stage of the converter design.

This paper presents two approaches to semiconductor power loss analysis in Modular Multilevel Converters (MMC) controlled without feedback of the switching cell capacitor voltage. The first one is a novel analytical approach - basing on an averaged model of the MMC. The second one is basing on detailed model in Matlab-Simulink - used as a reference for the analytical one. Analyses are performed for five MMC switching cells scenario. The analytical method has been proven as sufficient and fast solution for the MMC power losses estimation.

An active power filter based on a three-level neutral point clamped T-type converter with LCL input filter is presented in the paper. The main goal of the paper is the analysis of a control system that ensures independent control of a current in each phase. The presented control method of the filter allows reactive power compensation and/or a higher harmonics reduction to be achieved in each phase independently, with the possibility of control tan (φ) coefficient. This allows the power flow between the phases to be minimalized and reduces the RMS values of filter currents without the need to balance grid currents. The analysis presents the possibility of an operation in different modes, which was verified by experimental results. The results have been obtained in a 20 A_RMS laboratory system described in the paper. The results reveal relatively low power losses, which are a feature of the selected three-level T-type topology. Additionally, that topology, when compared to a two-level one, ensures the reduction in current ripples with the same parameters of passive components.

Today, to use home automation, intelligent home controls or remote controls in the office, electronic equipment is moving away from wireless communication in favor of Power Line Communication (PLC). In the standard PLC solutions, the corrections that result from error transmissions are based on complex digital modulation methods and algorithms for validating the transmitted data without paying attention to the causes of the errors. This article focuses on the implementation of a filtering system for interference and signals in the 120–150 kHz band (CENELEC band C), which is injected into the network by transmitters. Such a filter separates the desired signal from the interference that is occurring in the network, which can result in communication errors. Moreover, when used properly, the filter can be used as a subsystem separation element. The paper presents the requirements, design, construction, simulation and test results that were obtained under actual operating conditions. It is possible to use less complex methods for correcting errors in transmission signals and to guarantee an improvement in the transmission rate using the proposed filter system.

The paper presents the dc-link voltage balancing method for a five-level hybrid asymmetric multilevel converter based on a neutral point clamped (NPC) converter with H-bridge (HB) converters. The considered converter, which is referred to as NPC-HB, is treated in this paper as a modification of the classic three-level NPC converter. It improves the harmonic performance of output voltage compared to the NPC converter. This improvement is made by increasing the number of levels in the converter output voltage. Nevertheless, due to the use of floating H-bridge converters inside the NPC-HB topology, the dc voltage balancing method is implemented. Basing on the converter ac side current and HB converter dc link voltage, the proposed method modifies the PWM modulation scheme in both NPC and HB converters. This modification is applied to each switching period while the converter output voltage reference is kept unchanged. Such modulation scheme is characterized as robust and guaranteeing the low harmonic content in the output voltage. Other dc voltage balancing methods of the hybrid NPC-HB converter are compared in this paper. The proposed method is experimentally verified.

The aim of the paper is the evaluation of the advanced-neutral-point-clamped (ANPC) converter with two SiC MOSFETs and four Si IGBTs per a single phase leg. The main focus is put on the high switching frequency operation capability. Power loss calculation results of ANPC converter operating with 30 kHz switching frequency are presented. Both switching and conduction losses are evaluated, as well as power loss distribution among semiconductor devices. The results are compared to the conventional neutral-point-clamped (NPC) converter.