Solving the buffer allocation problem (BAP) in long production lines is difficult because it is an NP-hard problem. In this paper, we propose a new approach to solve the BAP for long series-parallel unbalanced production lines with the objective of minimising the average work-in-process subject to a throughput rate constraint. Instead of directly optimising a long line, this method decomposes the original long line into several small decoupled subsystems and adds relation condition variables between the subsystems. After several iterations between subsystem optimisation and condition updating, this method can obtain the optimal or near-optimal solution of the original system with a significantly improved computational efficiency. Extensive numerical experiments demonstrate the accuracy and efficiency of this approach. Finally, several examples and a multi-factorial experimental analysis are provided to show the influence of the decomposition strategy, initial values, and parameters of the target systems on the performance of the proposed method.

Simultaneous optimisation of machines and buffers in a large series-parallel production line is an NP-hard problem. The formulated optimisation model in this study is used to minimise the total investment cost subject to the desired throughput rate and cycle time by optimising the machine types, number of parallel machines, and buffer capacities. To solve this kind of design problem, a decomposition-coordination method is proposed to efficiently and accurately generate allocation solutions for large production lines. The proposed method includes two iterative processes: the decomposition process decouples the original line into several small lines and optimises them separately, while the coordination process ensures that the optimisation problems of the decomposed lines are similar to the corresponding part of the original. The performance of this approach is demonstrated through numerical experiments by comparisons with the simulated annealing algorithm and non-dominated sorting genetic algorithm-II. Finally, the sets of numerical results and a multi-factorial experimental analysis illustrate the influences of target system parameters on the resource configurations.

The acceleration architecture of transposed convolution layers is essential since transposed convolution operations, as critical components in the generative model of generative adversarial networks, are computationally intensive inherently. In addition, the pre-processing of inserting and padding with zeros for input feature maps causes many ineffective operations. Most of the already known FPGA (Field Programmable Gate Array) based architectures for convolution layers cannot tackle these issues. In this paper, we firstly propose a novel dataflow exploration through splitting the filters and its corresponding input feature maps into four sets and then applying the Winograd algorithm for fast processing with a high efficiency. Secondly, we present an underlying FPGA-based accelerator architecture that features owning processing units, with embedded parallel, pipelined, and buffered processing flow. At last, a parallelism-aware memory partition technique and the hardware-based design space are explored coordinating, respectively, for the required parallel operations and optimal design parameters. Experiments of several state-of-the-art GANs by our methods achieve an average performance of 639.2 GOPS on Xilinx ZCU102 and 162.5 GOPS on Xilinx VC706. In reference to a conventional optimized accelerator baseline, this work demonstrates an 8.6× (up to 11.7×) increase in processing performance, compared to below 2.2× improvement by the prior studies in the literature.

In recent years, long short-term memory (LSTM) has been used in many speech recognition tasks, due to its excellent performance. Due to a large amount of calculation and complex data dependencies of LSTM, it is often not so efficient to deploy on the field-programmable gate array (FPGA) platform. This paper proposes an LSTM accelerator, driven by a specific instruction set. The accelerator consists of a matrix multiplication unit and a post-processing unit. The matrix multiplication unit uses staggered timing of read data to reduce register usage. The post-processing unit can complete various calculations with only a small amount of digital signal processing (DSP) slices, through resource sharing, and at the same time, the memory footprint is reduced, through the well-designed data flow design. The accelerator is batch-based and capable of computing data from multiple users simultaneously. Since the calculation process of LSTM is divided into a sequence of instructions, it is feasible to execute multi-layer LSTM networks as well as large-scale LSTM networks. Experimental results show that our accelerator can achieve a performance of 2036 GOPS at 16-bit data precision, while having higher hardware utilization compared to previous work.

In recent years, Convolution Neural Networks (CNNs) have been widely applied to some artificial intelligence (AI) systems such as computer vision. Among many existing hardware accelerators, FPGA is regarded as a suitable platform for the implementation of CNNs because of its high energy efficiency and flexible reconfigurability. In this paper, a parameterized design approach is proposed to explore the maximum parallelism that could be possibly implemented in mapping a CNN algorithm onto targeted FPGA resources. Four types of parallelism are employed in our parameterized design to fully exploit the processing resources available in FPGA. Meanwhile, a hardware library consisting of a set of modules is established to accommodate various CNN models. Further, an algorithm is proposed to find the optimal level of parallelism dedicated to a constrained amount of resources. As a case study, the typical LeNet-5 is implemented on Xilinx Zynq7020. Compared with the existing works using the high-level synthesis design flow, our design obtains higher FPS and lower latency under the premise of using fewer LUTs and FFs.