The acceleration architecture of transposed convolution layers is essential since transposed convolution operations, as critical components in the generative model of generative adversarial networks, are computationally intensive inherently. In addition, the pre-processing of inserting and padding with zeros for input feature maps causes many ineffective operations. Most of the already known FPGA (Field Programmable Gate Array) based architectures for convolution layers cannot tackle these issues. In this paper, we firstly propose a novel dataflow exploration through splitting the filters and its corresponding input feature maps into four sets and then applying the Winograd algorithm for fast processing with a high efficiency. Secondly, we present an underlying FPGA-based accelerator architecture that features owning processing units, with embedded parallel, pipelined, and buffered processing flow. At last, a parallelism-aware memory partition technique and the hardware-based design space are explored coordinating, respectively, for the required parallel operations and optimal design parameters. Experiments of several state-of-the-art GANs by our methods achieve an average performance of 639.2 GOPS on Xilinx ZCU102 and 162.5 GOPS on Xilinx VC706. In reference to a conventional optimized accelerator baseline, this work demonstrates an 8.6× (up to 11.7×) increase in processing performance, compared to below 2.2× improvement by the prior studies in the literature.

Off-chip memory, such as DRAM, its access energy cost is orders of magnitude higher than other operations such as multiply and accumulate, thereby dominating the system energy consumption. Therefore, optimizing the access of the off-chip memory is crucial to further improve the energy efficiency of the deep neural network (DNN) accelerator. Towards this, this brief proposed an adaptive scheduling algorithm to minimize the DRAM access. Compared with the previous works, it can not only dynamically determine the data partition and the data type that will be reused, but also considered the constraints between adjacent layer, that is, if the output feature map of $i$ th layer is divided into N parts, the output feature map of $i+1$ th layer can only be divided into N parts or write back to the off-chip memory. Therefore, a minimize and realizable memory access solution can be obtained. Choosing 3 popular networks UNet, VGG-16 and MobileNet as benchmarks, the experiment results show that our scheduling algorithm can achieve a $34.46\% \sim 93.42\%$ reduction in energy consumption of DRAM access and a $34.34\% \sim 93.37\%$ reduction in DRAM access latency when compared to previous works.

A fast-locking digital delay-locked loop (DLL) is presented in this paper. By adopting a novel high resolution Time-to-Digital Converter (TDC), the time for generating fine-tuned codes is reduced to two clock cycles. Thus the total locking time is greatly reduced to 8 input reference clock cycles and remarkably shortened by 80% to 94.6% compared to previous closed-loop architectures. The proposed DLL has been fabricated in a 0.13μm CMOS technology and operates from 80MHz to 450MHz. The measured RMS and peak-to-peak jitters are 2.3ps and 10ps respectively.

Conventional SPICE-like simulators are not adequate for the noise simulation of the chopper amplifier, which typically has no DC operating point. This paper discusses the noise properties of the chopper amplifier in both time domain and frequency domain and presents a method of simulating chopper amplifier noise behavior with the RF simulator-SpectreRF. The simulation results for a designed circuit are given. A comparison between the simulation and the calculation results shows effectiveness and efficiency of this method in dealing with chopper amplifier noise simulation