The rising demand for increased integration and higher power outputs poses a hidden risk to the long-term reliable operation of third-generation semiconductors. Thus, the power cycling test (PCT) is widely regarded as the utmost critical test for assessing the packaging reliability of power devices. In this work, low-thermal-resistance packaging design structures of SiC devices are introduced, encompassing planar packaging with dual heat dissipation, press-pack packaging, three-dimensional (3D) packaging, and hybrid packaging. PCT methods and their control strategies are summarized and discussed. Direct-current PCT is the focus of this review. The failure mechanisms of SiC devices under PCT are pointed out. The electrical and temperature-sensitive parameters adopted to monitor the aging of SiC devices are organized. The existing international standards for PCT are evaluated. Due to the lack of authoritative statements for SiC devices, it is difficult to achieve comparison research results without consistent preconditions. Furthermore, the lifetimes of the various packaging designs of the tested SiC devices under PCTs are statistically analyzed. Additionally, problems related to parameter monitoring and test equipment are also summarized. This review explores the broader landscape by delving into the current challenges and main trends in PCTs for SiC devices.