Extensive research has demonstrated that memristors or trigonometric functions can enhance the complexity of discrete chaotic maps. This article introduces a four-dimensional trigonometric-based memristor hyperchaotic map (4D-TBMHM). By combining discrete memristors, sine, and cosine, the 4D-TBMHM exhibits complex dynamical behaviors. Bifurcation and multistability phenomena are demonstrated using numerical methods. The 4D-TBMHM demonstrates symmetric or attractor self-growth based on iteration length for various system control parameters and initial states, and its complicated complex fractal structure and exemplary performance metrics are also highlighted. Furthermore, an attractor hybrid control, capable of arbitrary positioning and shaping, is proposed. An field-programmable gate array (FPGA)-based hardware prototype is developed, and the attractors are experimentally captured. Moreover, by combining 4D-TBMHM with an arrayed linear feedback shift register, an ultra-fast pseudorandom number generator (UFPRNG) with a throughput of 195.2 Gbps is achieved on an FPGA, surpassing contemporary techniques. Last, the generated UFPRNG is employed for 2.8 Gbps signal generation with noise, and experimental results illustrate its remarkable real-time capability and the PRNG's inherent randomness, facilitating signal generation with any signal-to-noise ratios.

Plenty of source-free domain adaptation (SFDA)-based diagnosis approaches have been explored to tackle distribution shift and data privacy protection. Nevertheless, these approaches do not consider the uncertainty and large distribution characteristic of target predictions in time-varying conditions. Hence, their effectiveness is only suitable for scenarios with stable data distribution. Therefore, a new SFDA paradigm named source-free progressive subspace calibration (SFPSC) is developed to enhance model adaptation in complex dynamic data structures. In SFPSC, the CAS-Softmax is first constructed to suppress the overfitting of the source model, improving the mismatch of target samples. A new progressive pseudo-label selection strategy is designed for the training phase of model adaptation to gradually leverage easy-to-learn samples and guide the self-correction of hard-to-learn ones. Moreover, the scale robust subspace calibration is proposed to explicitly reduce the cross-domain distribution discrepancy. Finally, Extensive experiments on a laboratory gearbox and an actual equipment bearing validate the effectiveness and advantage of the proposed SFPSC.

Fractional order memory elements (FOMEs), which exhibit marked memory and nonlinear characteristics, have found broad utilization across an array of interdisciplinary fields. Unfortunately, a significant impediment to their integration into engineering applications is the scarcity of commercially available nanomaterial-based FOMEs. In this paper, we propose a hardware architecture with high FPGA resource utilization efficiency based on the Grünwald–Letnikov approximation and sampling theorem. This architecture can simultaneously realize three fractional calculus (FC) algorithms: the fixed window length (FWL), K-piecewise linear function ( $K$ PLF), and FWL& $K$ PLF without modifying the FPGA binary file. The method proposed in this paper has lower resource consumption, fewer memory requirements, and higher computational performance, resulting in lower step length by $10^6$ and higher operating frequencies compared with existing methods. Moreover, we design an FC experimental platform based on a digital oscilloscope that is capable of realizing FOMEs of any order by modifying parameters. In addition, a universal digital circuit of FOMEs is designed in FPGA, which helps to directly display signals at both ends of FOMEs in the digital domain, avoiding interference from circuit noises. Hardware experiments and digital simulations show that the proposed FPGA-based FOMEs hardware circuit method has high precision and reconfigurability, which further accelerates the engineering application of FOMEs.

The efficiency of the hardware implementations of fractional Kalman filter (FKF) heavily relies on the efficiency of realising the fractional‐order derivative operator. In this paper, a generic software and hardware implementation of the FKF based on the Grunwald–Letnikov approximation is proposed and verified on a field‐programmable gate array. The main advantage of this particular realisation is its resource saving capability on both software and hardware components (e.g. digital signal processing chips), and this enables fast and efficient real‐time computation of the FKF. Furthermore, the performance of the FKF is evaluated via studying the mean square boundedness of the filtering error. At last, a mass‐spring‐damper example is implemented via Matlab simulations to verify the applicability of the proposed approach and moreover, a hardware experiment is also conducted to demonstrate the advantage of resource saving.