Extensive research has demonstrated that memristors or trigonometric functions can enhance the complexity of discrete chaotic maps. This article introduces a four-dimensional trigonometric-based memristor hyperchaotic map (4D-TBMHM). By combining discrete memristors, sine, and cosine, the 4D-TBMHM exhibits complex dynamical behaviors. Bifurcation and multistability phenomena are demonstrated using numerical methods. The 4D-TBMHM demonstrates symmetric or attractor self-growth based on iteration length for various system control parameters and initial states, and its complicated complex fractal structure and exemplary performance metrics are also highlighted. Furthermore, an attractor hybrid control, capable of arbitrary positioning and shaping, is proposed. An field-programmable gate array (FPGA)-based hardware prototype is developed, and the attractors are experimentally captured. Moreover, by combining 4D-TBMHM with an arrayed linear feedback shift register, an ultra-fast pseudorandom number generator (UFPRNG) with a throughput of 195.2 Gbps is achieved on an FPGA, surpassing contemporary techniques. Last, the generated UFPRNG is employed for 2.8 Gbps signal generation with noise, and experimental results illustrate its remarkable real-time capability and the PRNG's inherent randomness, facilitating signal generation with any signal-to-noise ratios.

This study introduces a two-dimensional sine-based hyperchaotic map (2D-SBHM), which leverages the boundedness and periodicity of sinusoidal functions to enhance chaotic performance. The 2D-SBHM exhibits multiple fixed points, with variations in system parameters (SPs) inducing diverse bifurcation behaviors. Numerical analysis reveals a maximal chaotic range of [-40, 40] and a high permutation entropy of 6.433, outperforming several existing 2D sine-based maps in stochastic metrics. The coexistence of attractors, including heterogeneous and homogeneous types derived from SPs, is explored. Four cases of homogeneous attractors generated from initial states are presented. A modular arithmetic method is proposed for generating homogeneous attractors, allowing the creation of attractor sets in quantities such as 3, 5, 15, 20, or 30. Furthermore, a high-precision hardware implementation strategy using FPGA and DAC architectures is developed, enabling theoretical calculations for oscilloscope amplitude scaling and display area. An FPGA-based hardware platform is constructed to verify the proposed approach and realize a pseudo-random number generator with a throughput rate of 2.8 Gbps. To the best of our knowledge, this work represents the first demonstration of arbitrary homogeneous attractor generation in a discrete chaotic map using modular arithmetic, coupled with the first high-precision hardware implementation of chaotic attractors.