Hardware security and trust have become a pressing issue during the last two decades due to the globalization of the semi-conductor supply chain and ubiquitous network connection of computing devices. Computing hardware is now an attractive attack surface for launching powerful cross-layer security attacks, allowing attackers to infer secret information, hijack control flow, compromise system root-of-trust, steal intellectual property (IP) and fool machine learners. On the other hand, security practitioners have been making tremendous efforts in developing protection techniques and design tools to detect hardware vulnerabilities and fortify hardware design against various known hardware attacks. This paper presents an overview of hardware security and trust from the perspectives of threats, countermeasures and design tools. By introducing the most recent advances in hardware security research and developments, we aim to motivate hardware designers and electronic design automation tool developers to consider the new challenges and opportunities of incorporating an additional dimension of security into robust hardware design, testing and verification.

Information flow tracking (IFT) is a fundamental computer security technique used to understand how information moves through a computing system. Hardware IFT techniques specifically target security vulnerabilities related to the design, verification, testing, manufacturing, and deployment of hardware circuits. Hardware IFT can detect unintentional design flaws, malicious circuit modifications, timing side channels, access control violations, and other insecure hardware behaviors. This article surveys the area of hardware IFT. We start with a discussion on the basics of IFT, whose foundations were introduced by Denning in the 1970s. Building upon this, we develop a taxonomy for hardware IFT. We use this to classify and differentiate hardware IFT tools and techniques. Finally, we discuss the challenges yet to be resolved. The survey shows that hardware IFT provides a powerful technique for identifying hardware security vulnerabilities, as well as verifying and enforcing hardware security properties.

The continuous improvement in the connectivity, automation and autonomy levels of Intelligent Connected Vehicles (ICVs) significantly increases the probability of potential security threats. Over-the-Air (OTA) is a promising technique for upgrading features of ICVs and enhancing their reliability and security against environmental disturbances as well as malicious attacks. To better understand the potential security risks and possible countermeasures, we survey research works in ICV security during OTA from cloud upgrade, terminal upgrade, and object upgrade. We also summarize existing methods in OTA upgrading techniques and systematically investigate the overall framework of OTA upgrading methods from the perspectives of Software-Over-the-Air (SOTA) and Firmware-Over-the-Air (FOTA).We further discuss possible mitigation strategies and open issues yet to be resolved in this research direction. This survey shows that OTA provides a powerful technique for upgrading the ICV features and improving ICV security.

High-level synthesis (HLS) allows hardware designers to think algorithmically and not worry about low-level, cycle-by-cycle details. This provides the ability to quickly explore the architectural design space and tradeoffs between resource utilization and performance. Unfortunately, security evaluation is not a standard part of the HLS design flow. In this article, we aim to understand the effects of memory-based HLS optimizations on power side-channel leakage. We use Xilinx Vivado HLS to develop different cryptographic cores, implement them on a Spartan-6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and information leakage through power consumption. We have two important observations and contributions. First, the choice of resource optimization directive results in different levels of side-channel vulnerabilities. Second, the partitioning optimization directive can greatly compromise the hardware cryptographic system through power side-channel leakage due to the deployment of memory control logic. We describe an evaluation procedure for power side-channel leakage and use it to make best-effort recommendations about how to design more secure architectures in the cryptographic domain.

The design of modern computer hardware heavily relies on third-party intellectual property (IP) cores, which may contain malicious hardware Trojans that could be exploited by an adversary to leak secret information or take control of the system. Existing hardware Trojan detection methods either require a golden reference design for comparison or extensive functional testing to identify suspicious signals. In this paper, we propose a new formal verification method to verify the security of hardware designs. The proposed solution formalizes fine grained gate level information flow model for proving security properties of hardware designs in the Coq theorem prover environment. Compare with existing register transfer level (RTL) information flow security models, our model only needs to translate a small number of logic primitives to their formal representations without the need of supporting the rich RTL HDL semantics or dealing with complex conditional branch or loop structures. As a result, a gate level information flow model can be created at much lower complexity while achieving significantly higher precision in modeling the security behavior of hardware designs. We use the AES-T1700 benchmark from Trust-HUB to demonstrate the effectiveness of our solution. Experimental results show that our method can detect and pinpoint the Trojan.

Security critical hardware devices in CPS must experience security testing including side-channel leakage detection, which aims to provide earlier assessment before coming into service. Due to the exponential nature of ESLS, performing fast and efficient leakage detection is a critical task in the context of security evaluation for DSE. However, the traditional method of leakage detection is always time-consuming and costly. To overcome this limitation, this article investigates the strategies of leveraging the emerging ML techniques to achieve faster and more effective leakage detection. A clustering-based methodology is proposed as an alternative method for first-order leakage detection. We further confirm the effectiveness and rapidity of the proposed method by launching clustering-based analysis on seven different benchmarks. The proposed method provides almost the same quality of results as the non-specific t-test while substantially reducing the efforts on security evaluation in CPS.